Commit Graph

14 Commits

Author SHA1 Message Date
Gerard Marull-Paretas 0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Sylvio Alves 245b8264e7 soc: esp32c3: update startup code to map IROM and DROM segments
This change updates startup code to setup MMU mappings

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-01-22 16:55:00 -05:00
Glauber Maroto Ferreira 1af506dd32 soc: riscv: esp32c3: drivers: flash: add support
to host SPI Flash driver.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-10-28 06:47:21 -04:00
Felipe Neves b97c2da2f2 interrupt_controller: intc_esp32c3: added intc driver
For esp32c3 and replaces the hardcoded interrupt
attaching procedures with this new driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-02 14:33:24 -04:00
Jim Shu f3e926b6d0 soc: riscv: esp32c3: apply CONFIG_RISCV_GP option
esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Jim Shu 97fa203330 Revert "arch: riscv: added support for custom initialization of gp register"
This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-18 05:18:55 -04:00
Sylvio Alves 1d219250bc soc: esp32c3: fix implicit declaration
replace HAL call to direct read reg function

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-09 13:15:47 -04:00
Felipe Neves 4a0b5ce277 soc: riscv: esp32c3: fix ble controller init
By appending the right link layer controller configurarion

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves 600f8c64e1 soc: riscv: esp32c3: use the new esp_rom prefix
For esp32c3 related ROM located functions instead
of esp32c3_rom.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves 2d1bdd86b6 soc: riscv: esp32c3: adds _PrepC to the startup code
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves 4c60d2ccc7 soc: riscv: esp32c3: add z_bss_zero in startup code
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves 132ab922a8 drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS
Also added maintainer to the entry

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves 7b09d031fa arch: riscv: added support for custom initialization of gp register
Plus added implementation for esp32c3 SoC.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves 5d736766ed soc: esp32c3: added initial soc support files for esp32c3
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00