Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
If I2C3 switches from GPH1/GPH2 to GPB2/GPB5, extend setting
is required.
Test: Accessing I2C is normal if I2C2, I2C3, I2C5 are switched.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Refactor the pinctrl nodes slightly so that the port devices are not
child of the main pinctrl node. This is because the pinctrl node is
being used as parent for pinctrl setting nodes itself, and having the
port nodes as child end up creating a circular depdency with the edt
child enumeration patch.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
When the alternate setting is configured as func3, in addition to
the setting of func3-gcr, some pins require external setting.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
D extension implies the F extension, so writing `rv32ifd` is redundant
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Sometimes, channel C may write wrong register to the target device.
This issue occurs when FIFO2 is enabled on channel C. The problem
arises because FIFO2 is shared between channel B and channel C.
FIFO2 will be disabled when data access is completed, at which point
FIFO2 is set to the default configuration for channel B.
The byte counter of FIFO2 may be affected by channel B. There is a
chance that channel C may encounter wrong register being written due
to the FIFO2 byte counter wrong write after channel B's write operation.
The current workaround is that channel C cannot use FIFO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add SHA256 accelerator support for it8xxx2 series.
This driver passes the following test:
tests/crypto/crypto_hash/
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
The current configuration is too long and will block soc from
entering sleep mode. This change was made to get better power
number on EVB.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
1. Increase sram to 256KB.
A block sram of SCAR0~15 is 4KB.
A block sram of SCAR16~19 is 16KB.
A block sram of SCAR20~23 is 32KB.
2. Removed the register of RVILMCR which has no effect.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The alternate pins of UART2 have been remapped, and the remapped
alternate pins must be added to the pinctrl map.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Add kscan pins gpio driver for KSI[7:0], KSO[15:0] pins that
they can be configured to gpio mode. These pins registers address,
bit fields and function are different from GPIO group, so I create
a new compatible driver for these pins.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The interrupt and watchdog registers of the it82xx2 will be
remapped, so these device nodes should be separated to
it81xx2 from it8xxx2. it8xxx2 dtsi are common settings
for it81xx2 and it82xx2.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit adds the support for host commands being transported
by the Serial Host Interface on the IT8xxx2 SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
The GCR, PINCTRL, I2C and WUC registers of the it82xx2 will be remapped,
so these device nodes will not be in the it8xxx2.dtsi, these should be
separated to create a it81xx2.dtsi.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Adding I2C FIFO mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
The I2C master supports two 32-bytes FIFOs, channel A and C
are supported now.
I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.52ms(2.4ms->1.88ms) compared to the original pio mode when the
frequency is 100KHz.
3. It is normal to read sensor data through I2C on Nereid's platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
All the of the ITE it8xxx2 devicetree compatiables are of the form
ite,it8xxx2-<DEV>. However the PECI device was ite,peci-it8xxx2,
rename the compatiable to match the pattern used everywhere else.
Signed-off-by: Kumar Gala <galak@kernel.org>
ITE EC chip it81202 and it81302 both have embedded integrated
pd module (support two usbpd ports), this is different from
standalone TCPC. To prevent cc pins leakage, we disable not
active ITE USBPD port cc modules, then cc pins can be used
as gpio if needed.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This mirrors #36499 and other PRs that added them for other
architectures.
This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.
The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).
While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.
Signed-off-by: Olof Johansson <olof@lixom.net>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Tim Lin