We only need a 'compatible' entry for the DK,
not the SoC and part-number. This commit fixes
this and aligns the nRF5340 PDK DTS with the
remainder of nRF-based boards.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Conditionalizes csi pinmuxes on CONFIG_VIDEO for all nxp boards
(kinetis, lpc, and imx families) to avoid possible conflicts between
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes display pinmuxes on CONFIG_DISPLAY for all nxp boards
(kinetis, lpc, and imx families) to avoid possible conflicts between
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes dac pinmuxes on CONFIG_DAC for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes can pinmuxes on CONFIG_CAN for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes ethernet pinmuxes on CONFIG_NET_L2_ETHERNET for all nxp
boards (kinetis, lpc, and imx families) to avoid possible conflicts
between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes pwm pinmuxes on CONFIG_PWM for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes adc pinmuxes on CONFIG_ADC for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes i2c pinmuxes on CONFIG_I2C for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes spi pinmuxes on CONFIG_SPI for all nxp boards (kinetis,
lpc, and imx families) to avoid possible conflicts between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Conditionalizes serial pinmuxes on CONFIG_SERIAL for all nxp boards
(kinetis, lpc, and imx families) to avoid possible conflicts between
peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Pins p0.02/p0.03 that were assigned to the i2c1 node are NFC pins.
Use p1.02/p1.03 instead, which are routed to the standard I2C location
in the Arduino header.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Conditionalizes pinmuxes on associated driver configs (CONFIG_SERIAL,
CONFIG_I2C, etc.) for the rv32m1_vega board to avoid possible conflicts
between peripherals.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
I2C1 used LED pins rather than the ones in the Arduino header
position. SPI2 used Arduino D0 for both SCK and MOSI; replace all
pins with D11-D13 which are the standard location for SPI on the
Arduino header.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Enables the adc instance and pinmux associated with arduino header pin
A2 on the frdm_k82 board. Adds adc to the board yaml to ensure we build
adc samples/tests for this board in CI.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
As a slow FPGA platform with max. freq < 25 Mhz,
the default CON_SYS_CLOCK_TICKS_PER_SEC=10000 is
not suitable. CON_SYS_CLOCK_TICKS_PER_SEC=100 is
a better value.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Map Arduino interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by Arduino.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Map mikroBUS interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by mikroBUS.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Adds support for a new SHIELD, Eth Click.
Mikro-BUS type shield supported in Zephyr.
Adds Kconfig for mikroe_eth_click shield.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DISK_ACCESS_STM32_SDMMC flag to for each SDMMC pinmux
configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2S flag to for each i2s pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_CAN flag to for each can pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DAC flag to for each dac pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_ADC flag to for each adc pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_PWM flag to for each pwm pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2C flag to for each i2c pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SPI flag to for each spi pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.
Fixes#25337
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This makes the up_squared board default to x86_64.
This also adds a new board, up_squared_32, for when 32-bit
is desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Given that the UP Squared has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Let the default value for SYS_CLOCK_HW_CYCLES_PER_SEC come from the
SoC instead. Furthermore, a default for HPET_TIMER didn't even make
sense since this timer doesn't do anything with the Kconfig value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
OpenOCD currently uses a single-bank STM32 configuration for the
B_L072Z_LRWAN1 board. This causes flashing to fail when the firmware
image is larger than the first bank. Switch to the dual bank
configuration to make this work.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Enable icount mode for qemu_xtensa platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for hifive1 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_a53 platform, The icount shift
value is selectd based on cpu clock frequency of this platform.
The virtual cpu will execute one instruction every 2^shift ns of
virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m3 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m0 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_x86 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Ioannis Glaropoulos