A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This can help find unused symbols. Those end up without a type if
'default' is used instead of 'def_bool', which generates a warning.
Search for "Kconfig.defconfig" in
https://docs.zephyrproject.org/latest/application/kconfig-tips.html for
a longer explanation.
Keep the 'def_bool' for the following symbols, which seem to be
deliberately defined only in Kconfig.defconfig files:
- ALTERA_AVALON_I2C
- ALTERA_AVALON_MSGDMA
- ALTERA_AVALON_PIO
- ALTERA_AVALON_QSPI
- ALTERA_AVALON_SYSID
- CLOCK_CONTROL_IMX_CCM
- CPU_EM4_DMIPS
- CPU_EM4_FPUDA
- CPU_EM4_FPUS
- FP_FPU_DA
- I2C_GECKO
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Charles E. Youse