We need the same logic for each SOC, instead of copypasting
things just put this in a common file. This approach still
leaves the door open for custom memory layouts if desired.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.
There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.
Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.
This also fixes a problem where an extra megabyte was being
added to the size of system RAM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rework x86 linker scripts to use DT_REG_ADDR/DT_REG_SIZE on
DT_CHOSEN(zephyr_sram) and DT_CHOSEN(zephyr_flash). As part of this
we remove the dts_fixup.h. Using DT_REG_SIZE means we don't have to
adjust the sizes by 1024.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
generated_dts_board.h is pretty redundant and confusing as a name. Call
it devicetree.h instead.
dts.h would be another option, but DTS stands for "devicetree source"
and is the source code format, so it's a bit confusing too.
The replacement was done by grepping for 'generated_dts_board' and
'GENERATED_DTS_BOARD'.
Two build diagram and input-output SVG files were updated as well, along
with misc. documentation.
hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml
update.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.
() Removes the x86_64:x32 architecture and SoC, and replaces
them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The previous linker script was barebones and non-standard. It is
replaced with a script conforms to the rest of the Zephyr arches,
utilizing include/linker headers and standard macros.
link-tool-gcc.h is updated to account for the "i386:x86-64" arch and
the generation of 64-bit ELF binaries.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This patch adds basic build infrastructure, definitions, a linker
script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit
ELF binary suitable for use with GRUB to minimally bootstrap an
Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly
be called a Zephyr kernel as it is lacking most of the glue logic,
but it is a starting point to flesh those out in the x86 tree.
The "kernel" builds with a few harmless warnings, both with GCC from
the Zephyr SDK and with ICC (which is currently being worked on in
a separate branch). These warnings are either related to pointer size
differences (since this is an LP64 build) and/or dummy functions
that will be replaced with working versions shortly.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
XIP support in x86 was something of a mess. This
patch does the following:
- Generic ia32 SOC no longer defines a "flash" region
as generic X86 devices don't have a microcontroller-
like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
The board definition must provide a flash region definition
that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
removed.
- qemu_x86 has a fake flash region added, immediately after system
RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
XIP by default, plus an additional test to exercise XIP on
qemu_x86 (which supports it but has XIP switched off by default)
The overall effect of this patch is to:
- Remove XIP configuration for SOC/boards where it does not make
any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
it off by default for other tests, to ensure it doesn't bit-rot
and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.
Fixes: #18956
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Removes very complex boot-time generation of page tables
with a much simpler runtime generation of them at bootup.
For those x86 boards that enable the MMU in the defconfig,
set the number of page pool pages appropriately.
The MMU_RUNTIME_* flags have been removed. They were an
artifact of the old page table generation and did not
correspond to any hardware state.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Andrew Boie