Generate kernel image in Intel Hex format when building for the nRF52.
Remove the additional step from the board doc file.
Change-Id: I619496f64037c2a0ac459ae05e549e01458e0f71
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Do not redefine the the pinmux configuration for the board, just use
the data directly. No other board will be using those, just the galileo.
Change-Id: If774bc5c4335021ae58a682224f092db23bc9f1b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move pinmux defintions under board/<board> and have all board
configuration in one single place.
Change-Id: I055b024384fae2938881b1c57d8ce7426e732e92
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If the CPU is ARC, define timestamp_serialize() to be an
empty macro so that this test builds properly.
Change-Id: I36f00dd429972b610c327cbe59bedb24b33553ed
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Used to say "ISR to back to". Now says "ISR back to".
Change-Id: I568306f6653096799ec22ea21cdb9ebee42ac359
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
It was found that the test latency_measure, when compiled
for microkernel, would fail on the ARC. This because the
trap handler, used by irq_offload, wasn't supporting thread switching.
This submission adds the code to do that, and the code size is
bigger only when CONFIG_MICROKERNEL is defined.
To keep code a bit smaller, there is a trick exploited here where
the AE bit is cleared in the STATUS32 register and in AUX_IRQ_ACT,
bit 1 is set, to make it appear as if the machine has interrupted
at priority 1 level. It then can jump into some common interrupt
exit code for regular interrupts and perform an RTIE instruction
to switch into the new thread.
test/latency_measure/microkernel now passes.
Change-Id: I1872a80bb09a259814540567f51721203201679a
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Moved setting of specific Cortex-M compiler flags in each SoC directory
unify setting them in the arch/arm/soc Makefile.
Add flags for Cortex M0, M0+, M1, M3, M4, and M7. However only
CONFIG_CPU_CORTEX_M3 and CONFIG_CPU_CORTEX_M4 are supported at this time
As part of this change converted Kbuild files for some SoCs into
Makefiles as the Makefiles would be empty otherwise.
Change-Id: Ie4e0178b141ca761ec482a610ae50e94fe58070f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce a soc-cflags, soc-cxxflags, and soc-aflags as a means for
SoC specific compiler flags to be set without manipulating Kbuild
options directly.
Change-Id: I2c8f5019fb237429e59717ef96bd4251a61dc1a5
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Quark D2000 uses the IRQ 10 for the APIC timer interrupt, this
cause a conflict with the "random" IRQ for the footprint benchmark
Change-Id: Iead18821af307832d54b0c9f3db5e52413ba670b
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
ecc_make_key declaration has random size of NUM_ECC_DIGITS * 2 but
definition has (and use) only NUM_ECC_DIGITS.
Change-Id: I18f0d7992b21a2ed7ed99851b1b795cff0a08a10
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
DHCP client support provided for IPv4 over ethernet.
Change-Id: Ia89bc4123842cf109813b80a90b70cf50cc52e0a
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
Provide pcap support for echo-apps with PCAP=<filename> option.
For pcap support:
make server NET_IFACE=qemu PCAP=sample.pcap.
without pcap support:
make server NET_IFACE=qemu
Change-Id: Iad90064e0c32134f9c2fda7b28e2cbca1e4e931c
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
The echo-server should work just fine even if the multicast
context cannot be get. By default there are only two contexts
so the multicast would fail always anyway and the program
would not run properly.
Change-Id: Ia9737cbda4a933a208aae020f055f0b6062b4f47
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Earlier default was 8, new default is 4.
Change-Id: I99c9d2aae465fd0feb968efa7417cd28bafd73b8
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Earlier default was 10, new default is 2.
Change-Id: I307a4abaad34223254fd32e1fd4357892a04a2d0
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Earlier default was 10, new default is 2.
Change-Id: I938449d840a244a13e9b9b954648577b76db00bc
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The network context is similar concept as network socket.
Depending on application use, the number of contexts can be
now tweaked. Default value is now 2, it was 5 earlier. Using
the lower number saves 241 bytes of memory.
Change-Id: I6e2a9f053c8c63163af6d6175783233f67553ae9
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This saves little over 4kb of memory.
Change-Id: I4dc3812b11de2736e2bdc17042e47fcdf5cf5491
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
User cannot select CSMA mac driver any more in order to save some
memory.
Change-Id: I7805a1c2028f60bc8a428bd5b8f891d540a14b6d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
For CMSIS we now have HAS_CMSIS which needs to be added to the
SoC definition.
Instead of changing the main Makefile we now include a sub-Makefile
with all related header and library paths that are hosted in
ext/
Move redifintion of LIB_INCLUDE_DIR later to get variables defined
in Makefile.toolchain.*
Change-Id: I9f90f90247c2a66b4565427b89d4e1d4dd5c9622
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
for GCC ARM Embedded
When compiling and linking Zephyr with GCC ARM Embedded,
the path to the libraries to be linked needs to be provided
explicitely for the correct variant to be linked in.
JIRA: ZEP-377
Change-Id: I745aa45c7dde12f1cc5c8ea4380b904e086ed94d
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Change the dev name from PWM to PWM_0. This will make it
consistent with other drivers and also fix the device binding
failure in the PWM sample app.
Jira: ZEP-395
Change-Id: I90b945a7e57700d384eaa52e5300c881a3251d83
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This will allow the driver to be fiber and task safe
Change-Id: I916d4ad67ab6f51f41f3d1136c105e4d1445de48
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This will allow the driver to be safe from fibers and task
Change-Id: I6c4c4fc387cf334f0287b8a02982be1941a311fd
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
For some security scenarios the GDT may already be setup and locked,
in which case the kernel trying to set it again could lead to problems.
Change-Id: I727c1d213479f46a4bb6f0c04a9096131e10b3e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The TX fifo threshold is pretty arbitrary.
Set this too big and too many interrupts will occur
for no good reason. Set it too small, and latency
in the SPI transactions is introduced. User's will probably
have to tune this per their application and SPI frequency, etc.
I think setting this to 50% is a good guess for now.
Change-Id: Ib325d40bc7ee10473d99443b3b3cd00fd6e4b95f
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Disabled bluetooth test for STM32F103RB SOC because there is not
enough RAM space for the test.
Change-Id: I9f097d9201ed659c4970b67f42c570331b92bad8
Signed-off-by: Javier B Perez <javier.b.perez.hernandez@intel.com>
Enable warning about updating the MAINTAINERS file when new
files are being added.
Change-Id: I3b13ca25cd01e3254fd4b9e169546a395ebfcacd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Still WIP. Give statistics on memory/flash usage.
Run:
make BOARD=<board> ram_report
or
make BOARD=<board> rom_report
Change-Id: I6b0aee09b89275e12f1cde863d2c0f5b8dfd0409
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The ethernet driver generates a lot of spurious interrupts.
These spurious interrupts have two sources:
1) The Mac Management Counter (MMC) module generates a lot of interrupts
(GMI - bit 27 of the status register). Unfortunately the Interrupt
enable register doesn't allow us to enable/disable it (bit 27 is
reserved). Therefore the only way to mask this interrupt is to mask
all the MMC interrupts (register REG_MMC_RX_INTR_MASK,
REG_MMC_TX_INTR_MASK and REG_MMC_RX_IPC_INTR_MASK). By default
these interrupts are not masked.
2) The RX interrupt is not correctly acknowledged. According to the
datasheet, NIS is a sticky bit and must be cleared (by writing 1
to this bit) each time a corresponding bit, which causes NIS to
be set, is cleared.
Change-Id: I2033973849d87cddc328c65d0d4ad36b5a0c934e
Signed-off-by: Sebastien Griffoul <sebastien.griffoul@intel.com>
This adds simple tab completion for shell use convenience.
Change-Id: If90ded32fb5044741232933d2cb0ce626227d025
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
Carles Cufi