The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows
the riscv PLIC specification as defined in the riscv privilege
architecture specification.
It provides implementation for the riscv PLIC APIs as
required by the riscv-privilege SOC Family for SOCs providing
support for the RISCV_HAS_PLIC config.
Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In some cases we can either assume they are already masked
at boot and save some cycles, or the IOAPIC has configuration
from a prior boot stage that needs to be preserved.
Change-Id: I0c71ff0f01a6ee13a3b9c9e239d5a933d6cb6542
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a better choice of default; on Mint Valley using IRQ 0
for the timer collides with the DMA Error IRQ line.
Issue: ZEP-849
Change-Id: I14cb60fbe548488198813b2351e0ed1f07c2d07d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.
Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
This was never implemented on ARC/ARM and has been superseded
by irq_offload().
Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.
Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A special situation may occur when a processor raises its task
priority to be greater than or equal to the level of the
interrupt for which the processor INTR signal is currently
being asserted. If at the time the INTA cycle is issued, the
interrupt that was to be dispensed has become masked (programmed
by software), the local APIC will deliver a spurious-interrupt
vector. Dispensing the spurious-interrupt vector does not affect
the ISR, so the handler for this vector should return without an EOI.
Change-Id: I4cf4744bd6efd68b72e2c380269de4181dc80bd9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This module is based on the standard Local APIC and IO APIC source modules.
This modules combines these modules into one source module that exports the
same APIs defined by the Local APIC and IO APIC header modules. These
routine have been adapted for the Quark D2000 Interrupt Controller which has
a cutdown implementation of the Local APIC & IO APIC register sets.
Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Change DEBUG option into something more specific.
Change-Id: If1f421fbf7d234ad6bfac410697205d5d74548c0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removes the non-PIC disabling PIC code as the PIC is not a supported interrupt
controller. The PIC disabling code remains as it is needed to prevent the
generation of spurious interrupts from the PIC (see CONFIG_SHUTOFF_PIC).
Change-Id: Ic59aa17ab96f34685a5d7b5f24cab391de47edca
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Creating the IOAPIC and LOAPIC Kconfig options permits future commits to remove
those settings from the relevant board.h files.
Change-Id: Ie33c703f39c68d6e251d67b1c7cf75a0dd56a7e6
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
For as long as the IOAPIC and LOAPIC code is coupled (as it currently is),
enabling LOAPIC must select IOAPIC to be enabled as well. If future commits
separate the two, then the "select IOAPIC" can be dropped.
Change-Id: Ibe7e6b86e5add19b8b3cc68ebecce760d8914c86
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Selection of the IOAPIC requires that the LOAPIC be previously selected.
Change-Id: I13d95d4bb4ff02c1aebb0b5e573cb2b89dbe530b
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Jean-Paul Etienne