Commit Graph

2 Commits

Author SHA1 Message Date
Filip Kokosinski 2304a274e0 boards/riscv/m2gl025_miv: run tests on m2gl025_miv board by default
Issue #37006 highlighted that some tests are prone to not passing on
QEMU for 32-bit RISC-V. This commit enables running tests in Renode on
emulated 32-bit RISC-V m2gl025_miv platform as a double-check.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-08-30 09:32:36 -04:00
Nicolas Pitre 1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00