Commit Graph

1 Commits

Author SHA1 Message Date
Nicolas Pitre 7f74825958 riscv: add a qemu_riscv64 board
This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-09 09:11:45 -05:00