Smoke test was timing out in a WAIT_FOR macro on my up xtreme tgl board.
Enabling this sleep fixes it.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add a fairly simple test of the IPM-over-IPC driver. This hits all
the code, but works by implementing the host side of the protocol
partially in the C test code. The message is sent with an initial
payload, and then IPC commands from the firmware copy the data over
into the "inbox" region to simulate data being sent via the host.
Then we make sure it lands correctly as if the host driver had done it
directly.
This requries a new command in the cavstool script that will copy a
word from the "outbox" region to the "inbox" region (both are just
different SRAM windows, conceptually no different than the way the
script is already managing log output), but no significant surgery.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Now that we have easy access to code on the host, it's trivial to
check the clock against host timestamps with high precision.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On cAVS before 2.5, core power was controlled by the host. Add a
command to the cavstool.py script to allow us to do that under test
command so we can exercise multiprocessor startup/shutdown outside of
SOF.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This test obviously only works correctly if it's run from core 0 (the
only CPU that doesn't shut down). It was true essentially by
accident, but add some cpu_mask trickery to force things.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
It's useful for tests other than the IPC case to be able to
communicate with the script on the host, so generalize the interface
and move it to tests.h.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add code to exercise soc_adsp_halt_cpu() and validate the cores can be
restarted with the kernel z_smp_start_cpu() API.
Note that this interface is for 1.8+ devices only. On cAVS 1.5, the
core power is actually controlled by the host.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These are descended from a private collection of test rigs I've been
semi-curating. Getting cache, clock and memory space setup consistent
is mildly complicated on these devices and we've had bugs in all these
areas.
+ Check cache/uncache memory space setup, and make sure that the
incoherent cache is operating as expected.
+ Make sure all cores agree with clocking setup.
+ Quickly benchmark a two-instruction loop to detect messups with
instruction caching.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As Zephyr begins to absorb drivers for these platforms that had
previously been managed by the SOF app, there's a need for a rapid
board-specific smoke test to use during development.
This starts with the smp_boot_delay test (itself a unit test for a
SOF-derived feature) and adds a host IPC case (that needs to match
code in cavstool.py on the other side of the PCI bus!).
It will grow more features over time as needed.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Tom Burdick