Add fixup info for PWM nodes on STM32F0/F1/F3/F4/L4 and remove the
conflicting Kconfig symbols to fully switch STM32 PWM to device tree.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
The PendSV handler sits below the priority of other OS interrupts, but
it was inspecting kernel state before masking those interrupts out!
Move the locking to the top.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit removes the arm_mpu_enabled status flag in the ARM
MPU driver. This flag is not needed, because the value of the
MPU_CTRL register stays the same while the MPU is enabled, and
is cleared to 0 when the MPU is disabled. Therefore, we do not
need to prevent from having the enable or the disable operation
to be called multiple times.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In _arm_mpu_config provide a more detailed description of the
effect of MPU PRIVDEFENA flag when enabling the ARM MPU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
ARM Cortex-M0+, M3, and M4 MCUs have a fixed number of 8 MPU
regions, if MPU support is implemented. Therefore, we can
implement _get_num_regions() to return a constant, if CPU
is one of the above Cortex variants. _get_num_regions() is
invoked often in the code, so this solution increases processing
efficiency. A sanity check is implemented in arm_mpu_init(), to
ASSERT if the number of regions provided by hardware does not
match the expected (default) value.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commits adds a dependency for ARM_MPU on !CPU_CORTEX_M0,
so an accidental selection or ARM_MPU in ARM Cortex-M0 MCUs
will signal a K-config warning.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The original implementation of CONFIG_THREAD_MONITOR would
try to leverage a thread's initial stack layout to provide
the entry function with arguments for any given thread.
This is problematic:
- Some arches do not have a initial stack layout suitable for
this
- Some arches never enabled this at all (riscv32, nios2)
- Some arches did not enable this properly
- Dropping to user mode would erase or provide incorrect
information.
Just spend a few extra bytes to store this stuff directly
in the k_thread struct and get rid of all the arch-specific
code for this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
BUILD_OUTPUT_HEX was enabled by default for stm32 SoCs.
This should not be the default setting and besides it has no
effect because of 'default n' in misc/Kconfig that seems to
prevail.
Removing the 'default y' for stm32 to avoid confusion.
Fixes#8193
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On ARM, the __thread_entry struct pointer used when
CONFIG_THREAD_MONITOR is enabled was pointing to the initial exception
stack frame. That's not right: even though this contains all the same
info, it's not layout-compatible with the API struct. And once the
thread starts running, the ESF gets unwound and the memory recliamed
for the stack frame of the entry function!
Stuff the __thread_entry struct into its own memory at the bottom of
the stack like the other architectures do. Fixes#7541
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
PLL configuration options for i.MX RT SoCs were added in commit
3fd25c64c7, but the selects were
incorrectly added to the SoC defconfig rather than Kconfig.soc. This
resulted in the PLL options not being configured and the part not
booting properly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
An issue has been confirmed in CMSIS core header file in
SCB_EnableDCache when stack is in cacheable memory.
Issue report: https://github.com/ARM-software/CMSIS_5/issues/331
To workaround this issue by checking if Dcache's been enabled before
trying to enable it.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
- Remove clock gating code to be compatible with A1 silicon
- Remove PLL deinitialization code out of soc file
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
This commit moves the bit timing (PROP, BS1, BS2 segments and SWJ)
from Kconfig to the device-tree and fixes issue #7933
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
The r7 register is used as a frame pointer on ARM Thumb. As result, it
cannot be modified by the assembly code in functions using stack frame.
This commit replaces r7 by r8, which is a general purpose register.
Also it fixes#7704.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit fixes some minor function documentation issues
and comments' style in the NXP_MPU driver.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit inserts sanity checks every time we are performing
a (re)-configuration of one or multiple MPU regions, ensuring
that we do not attempt to configure an invalid region number.
Particulary for arm_mpu_config(), called during pre-kernel
initialization phase, we add a system ASSERT if we attempt
to initialize more regions that what is supported by hardware.
We do this to ensure the misconfiguration is detected early and
the system boot is aborted.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds an internal function to disable an MPU region.
The function includes an assert that the requested MPU region
number is a valid one. arm_mpu.c is refactor to use this
function in all cases where an MPU region needs to be disabled.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit enhaces the documentation of internal functions
in arm_mpu.c by explicitly stating that the caller needs to
ensure the validity of the supplied MPU region index. The
warning is required as these functions modify the ARM MPU_RNR
register, without checking themselves the validity of the
provided region number.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes some minor issues with coding style
and comment syntax in arm_mpu.c
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Change the zero latency interrupt priority level from 2 to 1.
This is the priority level that the kernel has reserved for the
zero latency IRQ feature by the _IRQ_PRIO_OFFSET constant.
The zero latency IRQ will now not be masked by the irq_lock function.
Update comments to reflect the priority levels reserved by the kernel.
Fixes: #8073
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Upon MemManage Exception, multiple status bits of MMFSR may be
set. This commit modifies the MPU Fault Handler, so that it can
inspect and display information from all error conditions,
instead of just the first error condition that is true.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Make MPU stack guard checks use the previously stored value
of the MemManage Fault Address Register, to ensure that the
address-under-check is valid.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Remove the dead code that was guarded by previously removed
Kconfig symbols for the sensortag board.
With b028a51542,
this fixes#7873
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
In some STM32 series, SPI LL headers where included under
CONFIG_CLOCK_CONTROL_STM32_CUBE flag definition.
Fix this and use CONFIG_SPI_STM32 instead.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Previously the directory core/cortex/mpu/ was getting included
on a hidden kconfig. Now this has been replaced with the Kconfig
CONFIG_ARM_CORE_MPU.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Enable the instruction cache by default in order to achieve a speedup of
up to 20% in code execution.
Cache can be disabled by setting the new NRF_ENABLE_ICACHE Kconfig
option.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
All the STM32L4 SoCs have a Cortex-M4F CPU, and thus have a FPU. Update
stm32l4/Kconfig.series to select CPU_HAS_FPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit fixes a compilation bug for an undefined variable
(mmfar), which is only conditionally defined. Instead of mmfar
we use the ARM register value directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Previously, there was no easy command-line solution for loading
a Zephyr program to (internal) flash.
So, the default development method was to load via gdb/openocd
to SRAM and debug from there, thus making the cc3220sf platform
non-XIP (CONFIG_XIP=n) by default.
With new openocd v 1.10 updates from TI (git.ti.com/sdo-emu),
the image can now be flashed and debugged via gdb/openocd,
so the default will be changed to XIP (CONFIG_XIP=y).
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.
Signed-off-by: Jun Li <jun.r.li@intel.com>
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
STM32Lx LPUART peripherals do not fit well into existing U(S)ART
port numbering scheme, so there will be two separate namespaces
in Kconfig: one for U(S)ARTs and one for LPUARTs.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
The metairq feature exposed the fact that all of our arch code (and a
few mistaken spots in the scheduler too) was trying to interpret
"preemptible" threads independently.
As of the scheduler rewrite, that logic is entirely within sched.c and
doing it externally is redundant. And now that "cooperative" threads
can be preempted, it's wrong and produces test failures when used with
metairq threads.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Refactor the _FaultDump of the default debug-level (2) to
provide the error code that indicates the fatal error reason.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Refactor FAULT_DUMP macro to obtain and store the fatal error
reason. Make non-default version of FAULT_DUMP (i.e. with
CONFIG_FAULT_DUMP level 1) to retrieve the default reason
for fatal errors (_NANO_ERR_HW_EXCEPTION).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Document that execution does not return from
_NanoFatalErrorHandler and _SysFatalErrorHandler.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The PPB, Peripheral, and any other I/O regions have been
removed, the Shareable options are only important with
unlocked dual cores. Just use the background mapping,
which is RWX for supervisor and no access for user mode.
The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.
Fixes#6896
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The PPB and Peripheral regions have been removed,
the Shareable options are only important with unlocked
dual cores. Just use the background mapping.
The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.
Related to #6896 and #7877
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:
- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller
Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Florian Vaussard