Commit Graph

10 Commits

Author SHA1 Message Date
Scott Worley bdaab8cfa0 drivers : timer : Add MEC1501 32KHz kernel timer driver
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2019-07-24 14:58:41 -07:00
Charles E. Youse c17c298749 drivers/timer/apic_timer.c: new local APIC timer for TICKLESS_KERNEL
The existing local APIC timer driver (loapic_timer.c) has bitrotted
and doesn't support TICKLESS_KERNEL, which is the preferred mode of
operation. This patch introduces a completely new driver, called
the APIC timer driver - the name is changed to allow the drivers to
continue to coexist in the short term, and also because "APIC timer"
isn't ambiguous (the I/O APICs do not have timers).

This driver makes no attempt to work with the MVIC timer as the
previous version did, because MVIC support is deprecated.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-27 07:20:54 -04:00
Filip Kokosinski c0c3cdfc57 drivers: timer: add LiteX timer driver
Add LiteX timer driver with bindings for this device.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-05-15 12:52:16 -05:00
Anas Nashif 3ae52624ff license: cleanup: add SPDX Apache-2.0 license identifier
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier.  Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.

By default all files without license information are under the default
license of Zephyr, which is Apache version 2.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-07 08:45:22 -04:00
Anas Nashif a93651085e boards: remove pulpino board
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-31 22:47:18 -05:00
Martin Benda 9653e15139 drivers: timer: Add RTC-based system timer for Atmel SAM0 series MCU
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.

Signed-off-by: Martin Benda <martin.benda@omsquare.com>
2019-01-29 17:58:05 +01:00
Marti Bolivar 502d306630 soc: riscv32: add RV32M1 SoC as openisa_rv32m1
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:

- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral

The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.

Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.

Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Anas Nashif 6b55598ad4 board: posix: add native_posix board definition
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Ramakrishna Pallala eb51886d8c drivers: timer: Add Altera shim driver for timer soft IP
Delete the native timer soft IP driver as we will be reusing
the Altera's HAL drivers for most of the soft IP's.

Add shim driver support for Altera timer system clock soft IP.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-11-17 07:46:40 -05:00
Sebastian Bøe 12f8f76165 Introduce cmake-based rewrite of KBuild
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.

Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.

This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.

For users that just want to continue their work with minimal
disruption the following should suffice:

Install CMake 3.8.2+

Port any out-of-tree Makefiles to CMake.

Learn the absolute minimum about the new command line interface:

$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..

$ cd build
$ make

PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html

Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00