Commit Graph

9 Commits

Author SHA1 Message Date
Anas Nashif 1e8afbfe5a cleanup: remove lots of references to unified kernel
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-12 12:37:11 -04:00
Leandro Pereira 27ea2d8eb7 arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr.  Some things are still
unconverted, mainly the exception table, and this will be performed
another time.

Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira 0e08b946de soc: esp32: Define __start as a C function
The first stage bootloader, part of the ESP32 ROM, already sets up
a stack that's sufficient to execute C programs.  So, instead of
implementing __stack() in assembly, do it in C to simplify things
slightly.

This ESP32-specific initialization will perform the following:

  - Disable the watchdog timer that's enabled by the bootloader
  - Move exception handlers to IRAM
  - Disable normal interrupts
  - Disable the second CPU
  - Zero out the BSS segment

Things that might be performed in the future include setting up the
CPU frequency, memory protection regions, and enabling the flash
cache.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Andrew Boie 51df312abc xtensa: merge crt1-*.S
We had two assembly files to prepare for entry into C domain,
one intended for the simulator and one intended for real boards.

- Both files merged into a single crt1.S for either simulated or real
  targets
- Extra logic to populate command line arguments from simulator removed,
  we don't use it.
- BSS zeroing logic from crt1-boards.S used
- Reference to missing reset-unneeded.S removed
- exit() implementation moved to fatal.c, now invokes a kernel panic
  if we are not running under the simulator

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Max Filippov a0fa4f3265 xtensa: use -mlongcalls instead of --longcalls
gcc only understands -mlongcalls form of this option, xcc understands
both. Use -mlongcalls for building with both xcc and gcc.

Change-Id: I93f65ccbc97429ae564f1986120b37ce205ee38c
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-13 20:33:28 +00:00
Anas Nashif b84dc2e124 kernel: remove all remaining references to nanokernel
Change-Id: I43067508898bc092879f7fe9d656ccca6fd92ab2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:10 +00:00
Mazen NEIFER aa1e95bfb2 Xtensa port: Moved XCC specific libraries out of genric Xtensa make file.
These libraries are unlikely to be uesd by GCC port and thus should not be in
a generic make file. Moved to specific toolchain make file.

Change-Id: Ib585b87700e409d678f7a5cb60cff67b6022ab05
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER b8cbd05e6b Xtensa port: Enable long calls for Xtensa vector table.
Change-Id: I2e4c9ca0742988eb9ab4ec2db7c81bc988212f2c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 1cded67f38 Xtensa port: Started port to for Xtensa cores family.
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.

Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:26 -08:00