This is hardware design so there is no need for it to be
configurable in kconfig.
Change-Id: Iff162f330aae8ef9a7139b6e7ed9bfa87f26189a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IRQ triggering condition should be specified by SoC as it is
a decision for hardware design. This should not be configurable
in kconfig.
The default is to be triggered on rising edge, just as the same
old kconfig did.
Change-Id: If59d88a30711eb8e03d9cc4f409055cefe1995c5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves those kconfig options which should be declared in
SoC or board header files instead. These are the one
that are tied to SoC or board and there is no need
for them to be configurable in kconfig.
Change-Id: I243d634f1a4a11dc8dc3530d95f93371015492b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch fixes drain of data left in UART Rx fifo.
uart_irq_tx_ready checks if Rx IRQ has been raised,
but because Rx IRQ is disabled this won't work even
if there are some data left in the UART buffers.
So simply uart_fifo_read is used to discard the data that
left in UART buffer.
Change-Id: I17f145ba58640650bafd3602412fc75229f39664
Signed-off-by: Mariusz Skamra <mariusz.skamra@tieto.com>
The PWM_QMSI_DEV_NAME and PWM_QMSI_NUM_PORTS options depend on PWM_QMSI
already so this patch removes the 'if PWM_QMSI' block since it is
redundant.
Change-Id: Iec303d27f088b96662fc58933eaa82fe9459cb59
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Fixes this built error:
zephyr/drivers/pinmux/quark_mcu/pinmux_board_quark_se_dev.c:149:19:
error: 'PINMUX_BASE_ADDR' undeclared (first use in this function)
_pinmux_defaults(PINMUX_BASE_ADDR);
Change-Id: I8302e4d6dbcf961e0c80f6bccf740a877bb364af
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The base addresses are SoC specific so there is no need to make
configurable via kconfig.
Change-Id: Iaf8444f77513255d5f0112af6710243aae09f066
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is to standardize the kconfig for specifying IRQ priority.
Change-Id: Iab10655c6fc6f17c0c6dd49cb7a4e74fabcf852c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is to standardize the kconfig for specifying IRQ priority.
Change-Id: I3a51b35e633dc7b1b841e9fa504bf0cfc0d4d575
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is to standardize the kconfig for specifying IRQ priority.
Change-Id: I05ae4033e2c5431ba2727c5d4000ef07e14739c8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most of the SoC and board Kconfig use the same values for
driver initialization priorities. So refactor them, and
discard duplicate ones.
The shared IRQ init priority was changed so that the kernel
default init and device init priorities can be standardized
across all SoC/boards. Same goes for DesignWare SPI driver.
This also changes the UART_CONSOLE_PRIORITY and
IPM_CONSOLE_PRIORITY to UART_CONSOLE_INIT_PRIORITY and
IPM_CONSOLE_INIT_PRIORITY, to standardize across all drivers.
Note that this does not take away the ability to override
those values. This just provides reasonable defaults such
that there is virtually no need to override.
Change-Id: Ibbd95d802c637df06f9a2fd48763ee1e6f4ff627
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The pinmux base address and number of pins are now defined in SoC or board
header files instead of specifying them in kconfig. This is because
the pinmux ties directly to the SoC (or board expanders) so the base
address and number of pins do not need to be configurable in kconfig.
Change-Id: Ib6090d7d022b491f3fe8f522858281504c6302bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is to follow how kconfig are defined for other SoC/boards.
Origin: refactored from exising file
Change-Id: Ic83b8a336f1910f17b3cf4e7f029fd076ba1b6bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The base address, IRQ line, chip select numbers, and clock
gating constants are static per SoC, so there is no need to
make them configurable in Kconfig.
Change-Id: I9f87ca29c28c38c42d4e4f1a3a41fa231f63ef03
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The base address and IRQ line are static per SoC, so there is no need
to make them configurable in Kconfig.
Change-Id: Ib78401ff136c29642356f5bda9d6cd3e5c98bece
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.
Change-Id: Ia252958d205e0100d1b92e2a12d4c22411bc94b9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.
Change-Id: I79b142414143bc5ef585d3136a00375233de1723
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are two major issues with the kconfig:
() Some of the config options have incorrect dependencies inside help
under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO.
() Since the SoC and board specific kconfig files are parsed first,
the help screen would say, for example, CONFIG_SPI is defined at
arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because
the actual config is defined in drivers/spi/Kconfig.
These cause great confusion to users of menuconfig/xconfig.
To fix these, the SoC and board defaults are now to be parsed last.
Note that the position swapping of defaults in this patch is due to
the fact the the default parsed last will be used.
And, spi_test is broken due to the fact that it requires
CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is
bypassed for now.
Origin: refactored and edited from existing files
Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is a temperature and atmospheric pressure chip. The datasheet is
available at:
https://www.adafruit.com/datasheets/BST-BMP280-DS001-11.pdf
Change-Id: I3406eb6c2c4da564757b8315323d0681d648b541
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
Added device power management hook infrastructure. Added
DEVICE_INIT_PM and SYS_INIT_PM macros that creates device
structures with the supplied device_ops structure containing
the hooks.
Added example support in gpio_dw driver. Updated the sample
app and tested using LPS and Device Suspend Only policies.
Change-Id: I2fe347f8d8fd1041d8318e02738990deb8c5d68e
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.
Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for task_sleep() and fiber_sleep() during the
system initialization. When CONFIG_NANO_TIMEOUTS defined,
before the k_server() starts, kernel uses nanokernel
system clock announce and task sleep functionality.
To give device drivers early sleep functionality, the system
clock has to start on SECONDARY initialization level, same
as most of the drivers.
Change-Id: Ie1d391945cd1cfb9a5dc199783c2d224eb1b0ef3
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Build with GPIO port E failed due to a missing comma.
Change-Id: Ib8fa7f4d03ed4f4c713a3a8a16ad3b37fcf6b0b7
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
This driver will be used when changing pinmux functionality during
runtime.
Change-Id: I8dc7b36af13202b97183c5ee05932567e7396276
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This moves the STM32 based boards (Nucleo F103RB and STM32 Mini A15) to
the "new" pinmux model.
Change-Id: I190df271a6b83fafeec0b281cd4ee7cf13d7e7db
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This driver can be used for multiple boards based on the Quark
microcontroller family, the exceptions are Quark X1000 and Quark D1000.
Change-Id: I4c6624293515e4bbf31ac94a7f57905b4a9ef13d
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This introduces the pinmux_dev driver for the Atmel SAM3X.
This driver implements what used to be the pinmux driver API, which
applications could use to modify the function of pins during runtime.
That functionality is now protected under the CONFIG_PINMUX_DEV option,
which should only be set during the early enabling of a new board, as
there is risk of damage to the board when misused.
Change-Id: I3aa00505d2771b53c41fe687c3e5230e804756be
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Setting the direction of a GPIO pin is not the responsibility of the
pinmux "board" initialisation. This should be left for the GPIO
utilising application.
Some macros that were only used when setting the pin direction are
removed.
Change-Id: I5b63d52446a27fe539c89f0639a8dcadf5ea9f80
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This driver doesn't provide any API, it only initializes the pinmux
controller to appropriate values depending on the board.
The first board to use this new infrastructure is the Arduino 101 board,
because it is alphabetically the first.
To better organize code for the different SoCs and boards, a "family"
level is created in the 'drivers/pinmux' directory. The Arduino 101
board is part of the Quark MCU "family".
The PINMUX_DEV configuration (and functionality) is removed for now, it
will be added back when the pinmux_dev drivers are (re)introduced, with
clearer semantics.
Change-Id: Idf5cc3caf6be620aa50828ae8fdc535df6caf458
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
ASSERT are put each time the timer0 limit register or the timer0 count register
is modified.
Change-Id: I38684d57803de285f4e26c68b449c71396e4c750
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
Add device driver for the gyroscope part of LSM9DS0 gyroscope.
Datasheet:
https://www.adafruit.com/datasheets/LSM9DS0.pdf
Change-Id: I25e0c8470c9b68c594bc4a0d2a9a13f8f41ee309
Signed-off-by: Murtaza Alexandru <alexandru.murtaza@intel.com>
When exiting from tickless idle uppon an external IRQ, the TICK timer
is set to fire at next TICK boundary. The current algorithm can lead
to a point that timer0_count register is higher than the timer0_limit
register.
In this situation the next TICK will fire after the counter has
wrapped and performed another cycle (~133 seconds).
This condition appears when the counter reaches the limit after the
Interrupt Pending flag is checked. At this point the counter is
automatically wrapped to 0, but is set just next to the limit to fire
at next TICK boundary by SW. At exit of the _timer_idle_exit function,
the timer handler is called, and sets the limit to 1 TICK. At this
point the situation is:
- limit register == 1 TICK
- count register is just below the old limit register and higher than
1 TICK
To fix this issue, at _timer_idle_exit, the limit register is always
set to 1 TICK and the count register set such as the next TICK fires
on time.
Change-Id: Ifa002809d426aa04109592e53d2b02a224f51101
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
The timer counts from 0 to programmed_limit included.
Change-Id: Ifc8585210c319f5452fafc911d4f6d72c4b91eaa
Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>
This patch fixes gpio_stm32 driver since it was merged with a few
occurrences of DEV_* error code.
Change-Id: I025e4f83d8ca07bc0fed7d3dcb9cce3b9d11c3fc
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Counter API and drivers were merged without fixing the new returning
error convention (errno.h codes). This patch fixes all occurrences of
DEV_* codes so -E* codes are used instead.
Change-Id: I85007e8565686b52121410badea547ed904460a0
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Moves config options for K64 into its own config file under its
own submenu.
Change-Id: I94ccac54709ab5ec8222daa8634818d9ebc3561d
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Makes K64 spi driver submenu available only if K64 soc is
selected.
Change-Id: I0ada8863a592f056dbe48e78d9374f2348dcac14
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Makes K64 pwm driver submenu available only if K64 soc is
selected.
Change-Id: I9959b4785c6deab01977f86bbbebe3d671a4eec7
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
According to the Core Sepcification, Advertising Interval Min/Max
shall not be set to less than 0x00a0 if ADV_SCAN_IND or ADV_NONCONN_IND
type is used.
Change-Id: I6c4ef4f73b82841c3a96694dda670cdd12a40a54
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Makes K64 gpio driver submenu available only if K64 soc is
selected.
Change-Id: I4097006a4dca718ed2da730fa85cd2ad9970f419
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Moves STM32 gpio driver under its own submenu, like atmel SAM3
and K64 gpio drivers.
Change-Id: Iebc474af9818a73275f99183d3f4788eea1e6ded
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Add support for use of HSE (incorrectly named PREDIV1)as input of PLL,
along with HSE bypass for stabilized external clock, and XTPRE
prescaler. Update PLL handling so that we do not unnecessarily enable
PLL clocks, instead enabling only the clocks sources that are required
as per user's configuration.
This change allows higher SYSCLK clock values, up to 72MHz.
Change-Id: Ia7c2be3ce11ac0de2efa664b20e7ab5fddd57a51
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Move re-enabling logic to the NBLE stack.
Change-Id: I1b895aa952a241dc41e2fc9faa2794a8c2c2d2db
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add driver for the HDC1008 temperature and relative humidity
sensor.
Datasheet:
http://www.ti.com/lit/ds/symlink/hdc1008.pdf
Origin: Original
Change-Id: I63cb4cdd94120b80d0d6f3205da073f0817c4f17
Signed-off-by: Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
This moves both the Bluetooth HCI and NBLE drivers under
"Bluetooth Drivers" category. This also adds a selection for
choosing Bluetooth stacks as the bulk of both HCI and NBLE stacks
cannot be compiled together.
Note that this does not move the source files. That should be
done in a separate change.
Change-Id: I32fa7097ada0fdc52bcc745adb78c7273f4023c6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add device driver for the BMA280 I2C-based triaxial accelerometer
sensor, which supports reading data from the accel-x, accel-y, accel-z
and temperature channels. The driver also has support for data-ready
and any-motion triggers.
Datasheet:
http://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMA280-DS000-11_published.pdf
Origin: Original
Change-Id: Iff7246d7dd4a9358ec7a71e8ffbcfcccd49e393c
Signed-off-by: Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
Signed-off-by: Teodora Baluta <teodora.baluta@intel.com>
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the gpio, i2c and watchdog shim drivers so they set the
CLK_PERIPH_CLK bit during driver initialization. Differently from Quark
SE, the peripheral clock gate bit (CLK_PERIPH_CLK) is not enabled by
default in Quark D2000. We have to explicitly set this bit in order to
properly initialize the device.
This issue has been masked so far because the CLK_PERIPH_CLK bit is set
when UART NS16550 driver is enabled. The UART NS16550 driver is enabled
by default for Quark D2000 so gpio, i2c and watchdog sample apps were
working just fine. But if we disable the NS16550 driver, these samples
applications stop working.
The remaining shim drivers already set the CLK_PERIPH_CLK bit during
initialization so there is no need to fix them.
Change-Id: I3f658da564f87e9d52092ce7aac423c7b3e0c890
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Add a driver for Independent Watchdog (IWDG) commonly found in STM32
MCUs. The driver has been tested on STM32F1 family MCU.
Change-Id: Idc6ac35990e46901a206b4af0ce3767eb4875de9
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add support for interrupts for input GPIO pins on STM32 MCUs. The SoC
support code is expected to provide an implementation of
stm32_gpio_enable_int() call.
Change-Id: I61bae54b8e044be4d7d8eb60c0c67b71f8c59553
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.
Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The patch extends STM32 serial port driver with support for IRQ API of
the common UART port driver API.
Change-Id: If105e8528ea4ed4181cc4af0c97c24aa874e69e0
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add driver for U(S)ART ports on STM32 MCUs. The driver implements basic
RX/TX functionality. Data transmission is implemented using polling. The
driver configures the port to use 8bit data transmission, 1 stop bit, no
parity control.
The driver exposes a public uart driver API and registers a single UART
device 'UART_0'. The device binds to USART1 peripheral and performs
required pinmux and clock control configuration. The device can be
initialized at the PRIMARY level, with default device priority.
The driver has been verified to work with a sample Hello World
application on a STM32F103 series MCU.
Change-Id: Iae103fcd8d2fb0a6c173cf141a68e17791255aab
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add necessary integration code enabling use of common STM32 pinmux
driver.
The alternate function listing currently consists of USART1 pins
only. The listing should be updated when support for more devices is
added.
Change-Id: Ic65aeea9df9aaea7636ecdd6996f56e6ef59dc2f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The driver implements a GPIO device interface for STM32 MCUs. Each SoC
must provide implementation of the follwoing calls:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(),
stm32_gpio_set(). Consult gpio_stm32.h header for details on semantics
of these calls.
The driver registers 5 devices, each corresponding to a single GPIO
port. The users can then access individual pins by using values
0-15.
Change-Id: Id236b5b75c9dd091018a50a7be3501c8591cd551
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add a common driver for pin control subsystem in STM32 MCU series. The
driver allows for selection of pin's function without the ability of pin
remapping.
The driver implements a pinmux driver API, with custom `func` and `pin`
encoding in API calls. The caller is expected to use STM32PIN() helper
macro for encoding port/pin numbers or using one of the provided
STM32_PIN_* defines.
The common driver requires SoC specific support to be implemented. The
SoC code must implement these calls: stm32_get_pin_config(),
stm32_get_port_clock(), stm32_pin_configure(). Consult pinmux_stm32.h
header for detailn on semantics of these calls.
The driver also requires board level integration. The call
stm32_board_get_pinconf() is expected to privide pin function
assignments for the target board.
Whenever an IO pin is being enabled, the driver will automatically
enable the clock for corresponding port. The driver does not implement
disabling of port's clock as this has potentially disruptive, as such
such operation should be done explicitly in the code.
The pin control module needs to be initialized before any other modules,
but after clock_control. For this reason, the driver is initialized by
default at PRIMARY level, with priority set to 2. The priority can be
changed through configuration.
Change-Id: I8cb746d0f3cad72cd50b3355fe6d93a9f469be25
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Current design of Nordic RPC requires strict firmware compatibility,
add check indicating if firmware is incompatible. At the moment we
allow to continue since something may work :).
Change-Id: Ie67d4a6509e53553ae6c41a2c8d2593ab20bdcfb
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Allow to use Non Resolvable Private Address (NRPA) in advertisement,
following NBLE change.
Change-Id: I9491cfcd2e981237c99e55773a8beaddaee8b730
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Update firmware version to 0317. Changes are mostly related to
advertising.
Change-Id: I3a438ad38e3c892e354f7ea59b99739153957f19
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This moves the kconfig options for each drivers into their own
submenus. This makes menuconfig easier to navigate.
Change-Id: I2bdc8c3b61e424248ffb65385a7eabc797d89684
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves the kconfig options for STM32F10X clock control driver
into its own submenu.
Change-Id: I9ef658defe85feab3dfdb3e329710cb48bbffd86
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Moves the Quark SE clock control into its submenu.
() Fixes the dependencies in the SoC default Kconfig
so the options are not displayed out of place in
menuconfig.
Change-Id: Ifdf06242be8ceed03c2c657c942875a5a7f2750e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Put the kconfig options for individual drivers into
their own submenus. This makes it easier to navigate.
Change-Id: I96b230c3236722c809337472f7efdc2dc1bafdee
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replaces old DBG calls by new SYS_LOG_... ones, likewise updates the
grove/Kconfig file to include new per-level logging control.
Change-Id: I638ffa915a760b4f188c1bfa2dc68e63cbf7e624
Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
() Moves config options for each controllers into their own
Kconfig files. This keeps upper level Kconfig from getting
too big.
() Options for each controller are moved under their own
submenus.
Origin: refactored from existing file
Change-Id: I77e92f72f8de85abaedfbe078283607b7c242c81
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Moves config options for each controllers into their own
Kconfig files. This keeps upper level Kconfig from getting
too big.
() Options for each controller are moved under their own
submenus.
Origin: refactored from existing file
Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Moves config options for each controllers into their own
Kconfig files. This keeps upper level Kconfig from getting
too big.
() Options for each controller are moved under their own
submenus.
() Adds the missing copyright to Kconfig.atmel_sam3.
Origin: refactored from existing file
Change-Id: I2dacd3d9b2bfa052c9e0c078ddffed40dbc2ddbf
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Moves config options for each controllers into their own
Kconfig files. This keeps drivers/gpio/Kconfig from getting
too big.
() Options for each controller are moved under their own
submenus.
() Re-named the device names to standard as "GPIO_0", "GPIO_1",
etc.
() Adds the missing copyright to Kconfig.atmel_sam3.
Origin: refactored from existing file
Change-Id: I7c531b0109ca5a6840d3abd9daa6bc784f15233d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Adds some comment to divide config options for easier
visual navigation.
() Put config under submenus to make all driver options
consistent with each other.
Change-Id: Ia219c5283e4fa394adf8b0ac03577a0fd033ec1c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The helper for analyzing (fiber) stack usage is in no way specific to
Bluetooth and will likely be of use to many other places as well. Move
it therefore to include/misc.
Change-Id: Iedb699dbe248aca305e387998d37bb339cfb0e21
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Move driver specific config options to separate Kconfig sub-files
as this is a more scalable approach when considering that multiple
sensor drivers will be added in the future.
Change-Id: Ia1d62afd628723be33868d6c1a956ca7b27eba88
Signed-off-by: Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
Quark AON counter and timer sub-drivers. They are based
on the QMSI drivers.
In order to enable this driver, the following options
must be set.
CONFIG_QMSI_DRIVERS
CONFIG_QMSI_INSTALL_PATH
CONFIG_COUNTER
Origin: Original
Change-Id: Idbeabfaef3408f4d645b0e64a337d7f5f0f357c7
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Add the public API for counter devices and the drivers infrastructure.
Origin: Original
Change-Id: If100fbc9b3d119ce2be6c131bd64dbeb4fe346f2
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This patch replaces all occurences of the macro DEV_NOT_CONFIG by
-EPERM at the driver level. This patch is part of the effort to
transition from DEV_* codes to errno.h codes.
Change-Id: I3054c8aa76319a58a2eec089b8a72bf301c85391
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_NO_SUPPORT by
-ENODEV at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I03007527367b03e6fd72a85004b7d3b81046a6a6
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_NO_ACCESS by
-EACCES at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: Ic7fd162b45e9ceb73141a164649b96eea9886873
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_USED by -EBUSY
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I21eb3ffe9bdfde98593dcf63c50a8bdcd376e49e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_CONF by
-EINVAL at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: Idae0d5af8dd780416977c9261a5fb6188c3aab64
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_OP by
-ENOTSUP at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I46aec3c65963018c479b01602e4a3eec8650eaff
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_FAIL by -EIO
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I0594ab5dbe667e074c250129e7c13ce512ac940f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_OK by the actual
value 0 at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I69980ecb9755f2fb026de5668ae9c21a4ae62d1e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
All driver APIs (i2c, spi, gpio, etc.) return 'int' type, but pinmux
APIs. So this patch changes the returning type from 'uint32_t' to
'int' from include/pinmux.h and fixes all pinmux drivers according.
Besides keeping consistency between all drivers APIs, this patch is
also applicable for the errno.h code transition. Pinmux drivers will
return negative errno.h codes so returning 'int' is more suitable
than 'uint32_t'.
Change-Id: I2a6e92d567a0e21fec363226da6197df94657d4b
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.
The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.
The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.
The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.
Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Extend the public API of clock_control driver with a function for
querying of clock rate driving given peripheral. This is useful when the
driver must calculate or configurae values that depend on the rate of
clock driving this subsystem.
A baud rate setting of UART port is an example of such operation. To
configure a particular baud rate the driver may need to set the internal
counters of UART port, where the actual value will depend on the clock
rate for this peripheral.
The implementation returns DEV_NO_SUPPORT for clock_control drivers that
do not implement such functionality.
Change-Id: I4e7ec96cd3678a4bb1ff289b0247488289310f2d
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Move quark_se clock control entries to separate file. This will help to
keep things organized once we add more clock control drivers.
Change-Id: Id8f4a94189ab5bbba9b6552777549cf426d79273
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Take into account btauth callbacks for finding out IO capabilities.
Change-Id: Ifc35a1919c7e4d1b5ebaace7f13744f9b977d7e8
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add skeleton to handle events generated when trying to set security.
Change-Id: If9635690d50dce22a35dd0d05d8cc5046edaafee
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Implement bt_conn_security() for NBLE. We call
nble_gap_sm_security_req() which shall do all needed job.
Change-Id: I5fdccc2ea3e88266db8f940dc453547d5ea51f59
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Refactor code to be aligned with upstream Nordic BLE RPC. There UUID
is used only for primary service and characteristics.
Change-Id: I8fa840570c2535a73aaa68793a45013faacc59da
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Correct error message sent to application using GATT API.
Change-Id: Ibf7f9f8943f7e11fd2cf6eaff7c2fabbcdcadba9
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Implement bt_gatt_indicate() and response to it
on_nble_gatts_send_ind_rsp().
Change-Id: Ibf427135c6385cb84f9fab4edeb3a21760a8702e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
For printing two octets handle use 0x%04x print format specifier.
Change-Id: Ia654d9f2a639cfb9d63647497b302205efab0869
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Update RPC to make it compatible with firmware 0309. Among other
changes mostly related to cleanup there is extra flag octet in
struct nble_discover_params.
Change-Id: Ib4dbe15a6919c251f14888090e2f1d91c150c5f2
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Implement bt_gatt_subscribe() function and handle subscriptions.
Change-Id: Ib6ea63a237413ffc65d8572b14d7912d4c7d2699
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This makes sure the CONFIG_GPIO_K64F_* kconfig options have correct
dependencies. Or else CONFIG_GPIO_K64F can be disabled, but all
the CONFIG_GPIO_K64F_{A,B,C,D,E} are enabled.
Same goes for SPI, FTM and pinmux.
Change-Id: I8d225dea714081b14b19006d61b8f3f6afafa5ee
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DesignWare GPIO options should really depend on whether
GPIO_DW is enabled.
Change-Id: I98b2964d6a0afdac89dc66a78342076afa6feec5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a menu to enclose all the shared IRQ kconfig options.
Change-Id: I8083204c53f60022c06e9c683fa9544fdc278f32
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Support for data-ready and near/far triggers is included. Datasheet the
sensor available at <http://www.semtech.com/images/datasheet/sx9500_ag.pdf>.
Origin: Original
Change-Id: Idd491a8bad7e119b0ed66e655955228ffdac6e76
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
The MCP9808 supports threshold triggering. Add support for this feature
in the driver and the sample application.
If triggering is activated, the driver can create its own fiber or use
the system-wide sensor fiber.
Origin: Original
Change-Id: Ie825a22245cb48cbdffba3049011e4d305975d53
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
The driver only supports simple temperature readings. It does not
support the alarm feature. Datasheet available at
<http://ww1.microchip.com/downloads/en/DeviceDoc/25095A.pdf>.
Origin: Original
Change-Id: I283e6697fc6947975323d280f5ff0ba625fac5a9
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
Making pinmux depend on GPIO breaks many tests and configurations
when running on real hardware. This should be added as local
configuration in the defconfig instead.
Change-Id: Ibbf1c9a3428ed692937383bf85218b0c120cbe44
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to documentation, there must be at least one cycle delay
between two consecutive writes of the DR register. Apparently, this is
true for reading too, though undocumented.
The read_dr() inline function is called as follows:
*(spi->rx_buf) = read_dr(info->regs);
which the compiler, with full optimizations on, turns it into:
ld_s r2,[r1,24] <- the spi->rx_buf
sr 0x80000000,[r4] <- this is the strobe bit write !!!
lr r4,[r4] <- this is the FIFO read!!!
stb r4,[r2] <- store the result
Unfortunately, the read from the FIFO is always 0 since the FIFO data is
not yet available.
During my investigations, I found that the following code works:
sys_out32(1 << 31, info->regs + 0xd);
*(spi->rx_buf) = sys_in32(info->regs + 0xd);
This does, basically, the same thing. But the compiler inserts an
instruction in between the write/read:
sr 0x80000000,[r4] <- write of the strobe bit!!!
ld_s r2,[r1,24] <- the pointer goes to r2
lr r4,[r4] <- read from FIFO!!!
stb r4,[r2] <- store the result
A single clock cycle between writing the register and reading seems
to be enough for the data to become available for reading.
This patch adds a nop in the read_dr() inline function.
Change-Id: I0c216d5738d5771835b1052e2e83363e8e3abf0c
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
This creates the QMSI comparator driver which is simply a shim driver
based on the comparator driver provided by QMSI BSP.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_AIO_COMPARATOR=y
CONFIG_AIO_QMSI_COMPARATOR=y
Origin of the file: Original
Change-Id: Iad01cb80f7bb1eff1710cd76cd0afeb70c311e04
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.
Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.
Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.
Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports line control and
driver command APIs.
The line control function supports the baud rate option only (LINE_CTRL_
BAUD_RATE) and, at the moment, the QMSI driver doesn't have any custom
command.
Change-Id: Icc10cb39b4077ed4ccfefb1f0feecec75b79d67c
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports different baud
rate configurations. The baud rate is set per UART controller via
menuconfig. The default baud rate is 115200.
Change-Id: Iad736d72bd309b8a33ab5d538251fce374e89fd2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.
This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y
This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.
Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This reverts commit 0d50329105.
This breaks sanitychecks in CI. The early_sleep kernel test case is failing
randomly.
Change-Id: I015f20699c052b4089076699fc0180945c4d3d16
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The driver should read the mac address from the chip but in
case of cc2520, the chip does not have it. So generate a
random mac address for this invocation of the device.
Change-Id: I2d0cf2ee70525e7f5e65da9fb8ceaa1a2dccecdd
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Now that the internal libc has the off_t type it's the natural choice
for the offset parameters in the flash API.
Change-Id: I69999999625b46634f6d3008fe1b3f82c17d357c
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This makes the ordering consistent e.g. with SPI, Bluetooth and
Networking APIs. This also follows the order of parameters in the
POSIX read/write APIs.
Change-Id: I4f11c8c90ccadf176d79f6a7bbd98aac61c26cf5
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
size_t is the natural type for any integer that describes a number of
bytes. For the actual data use void pointers to avoid callers having
to do explicit typecasts if the data doesn't originate in a uint8_t
array. Also use a const pointer for writing to avoid typecasts for
data that originates in a const location.
Change-Id: Idbfc14b2d61ca6189411b211c3727f857dbd4059
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Fix dependencies of K64 PWM config options so that they do not appear at
incorrect places in the menuconfig tree hierarchy.
Change-Id: Iea8077400a1bdf3ef1c38b3bf45b7a72373bd096
Signed-off-by: Maciek Borzecki <maciek.borzecki@gmail.com>
Add support for task_sleep() and fiber_sleep() during the
system initialization. When CONFIG_NANO_TIMEOUTS defined,
before the k_server() starts, kernel uses nanokernel
system clock announce and task sleep functionality.
To give device drivers early sleep functionality, the system
clock has to start on SECONDARY initialization level, same
as most of the drivers.
Change-Id: I5b3cf3da4c8d8398a966e901ab211f2fcee18dd6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Implement GATT write without response, no signing yet.
Change-Id: Id676202ab270cf3f0b06ede26dee2f84a9965e09
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Config options 'Clock Radio and 'Serial Delay' appeared out of ADC menu
due to a missing dependency on ADC_QMSI.
Change-Id: Ia1ca0d5a4ea676205a5928689c2adee9e26c2691
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Support for Freescale/NXP K64 SPI modules, limited to:
- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats
Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).
Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
PWM support using the Freescale K64 FlexTimer Module (FTM)
Change-Id: Iaad429c01bd877babba04e84d6a4679bd7e38120
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Interrupt and callback function support is added to the K64F GPIO driver.
The implementation is based on the Designware GPIO driver (gpio-dw.*).
Change-Id: Id88d06f748400f8f822ca98e098cb44a53678c38
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
K64 pinmux support is created as a normal driver.
As opposed to the Galileo board, the pin configuration options are
defined by the MCU and are not board-specific. Separate
platform/board-specific configuration code uses the pinmux driver for
the default pin settings. For FRDM-K64F, only the Arduino pins (22 of a
possible 160) are set up.
Some of the I/O pins routed to the Arduino header are also configured as
JTAG/SWD signals by default and are used by the OpenSDAv2 debug
interface. Therefore, a PRESERVE_JTAG_IO_PINS config option was created
for the FRDM-K64 platform to prevent the default pin settings from
re-configuring these pins.
The K64 MCU separates pin configuration and control, implemented in the
pinmux driver, from GPIO. This results in some cross referencing
between the K64 GPIO driver and the K64 pinmux driver due to the
dependencies of one on the other.
This pinmux driver also uses the expanded pinmux function/mode parameter
size to describe pin configuration options with bit fields for the K64,
including up to 8 pin functions, plus interrupt, pullup/down, drive
strength, open-drain and slew rate.
The following GCC warnings in the K64 pinmux driver are prevented when not
compiling with 'no-optimization' (-O0):
warning: 'gpio_dev' may be used uninitialized in this function
[-Wmaybe-uninitialized]
Change-Id: Ie5031d18750143bf895883058b3cd55fd9989fd3
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Implement GATT read reusing gatt_private to store GATT parameters.
Change-Id: Ie3c58a6272cc7cf380e4d3a04e45b191680d1ebe
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The pinmux API was modified to expand the meaning of the 'func' argument
to allow it to represent more than a pre-configured function. This was done
to reasonably accommodate a larger range of pin configuration options
offered by other MCUs, such as the Freescale K64 (up to 8 pin functions,
plus interrupt, pullup/down, drive strength, open-drain, slew rate, etc.).
This allows bit fields to be used to define various settings.
Change-Id: I2b216b822c6bae7133eed01c8c3339bb47b6c5db
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Basic driver support for the Freescale K64 GPIO module.
Note that only pin direction, read and write are supported.
Change-Id: I6587bb260197a00497be9ac991002e3dde54718d
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Daniel Leung