Commit Graph

70 Commits

Author SHA1 Message Date
Alexandre d'Alton eac563ef27 arc: remove unecessary instruction and doc
lp_count register can be store directly to memory, it is actualy done,
and the instruction that precedes it has no effect.

Change-Id: I8b8fee6abd6f08eea38dd1ab5bbe61c25a2a1f7d
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
2016-03-29 01:25:49 +00:00
Alexandre d'Alton f91e55b798 arc: implement stack checking
ARC CPU has stack checking feature that allows to trigger an exception
whenever the stack is incorrectly accessed.
This patch implements the stack_top and stack_base register updates on
context switches, and activates the Stack Checking bit of STATUS32
register when the CPU is in the context of a fiber or task.
As GCC accesses the non-yet allocated stack with frame pointer enabled,
this patch also add the omit-frame-pointer gcc flag in order to work
properly.

Change-Id: Ia9e224085a03bd29d682fb8f51f8e712f2ccb556
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
2016-03-29 01:25:49 +00:00
Ramesh Thomas bb19e6f82f power_mgmt: Make names consistent with new RFC
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.

Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-26 14:35:11 -04:00
Juan Manuel Cruz d151776e59 debug: thread monitor allow to access more thread information
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.

Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.

By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.

It also allows a task to access its kernel task structure
through the first parameter of the thread.

This allows a debugger application to access the information directly
from the thread context structures list.

Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
2016-03-11 22:11:39 +00:00
Andrew Boie 4a4e82b0c5 arc: remove CONFIG_SW_ISR_TABLE_BSP
It is semantically identical to CONFIG_SW_ISR_TABLE.

Change-Id: Iff0c47166ee6fb1fd8a0991a67bc863d45c32559
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie e2283a2c58 arc: move vector and sw isr table to core code
Change-Id: Iea7ce4248ff3aaba2a5736c5e50f17c7b8b344af
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie e444825ee3 irq: formalize external zephyr interrupt API
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.

Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.

Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-26 15:53:22 +00:00
Daniel Leung cb76f11259 arch/arc: fixes native C version of atomic_nand
Change-Id: I2f493e2c7cb841ef1273e628701d3b087d402e3f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:28 -05:00
Fabien Chereau 78b2670032 irq: added a check for dynamic IRQ table overflow
Change-Id: I0128f752f8e42ee38331fa937b7616354bf346e0
Signed-off-by: Fabien Chereau <fabien.chereau@intel.com>
2016-02-05 20:25:24 -05:00
Peter Mitsis a0e4568760 c++: Add extern "C" { } block to header files
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.

Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:22 -05:00
Andrew Boie 2a1ae3f436 ARM: ARC: put sw_isr_table in ROM by default
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.

At some point this config option broke, probably when static
interrupts were introduced into the system.

To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.

Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:21 -05:00
Andrew Boie d9cfbd5a61 interrupts: new static IRQ API
The interrupt API has been redesigned:

- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
  It will be used in situations where the new static irq_connect()
  won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
  exactly the same way as its dynamic counterpart. The old static irq
  macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
  generated inline with irq_connect()

ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.

Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:17 -05:00
Daniel Leung db2d48b66f arc: add atomic operations for ARC EM family processors
The ARC EM family processors do not support native atomic assembly
instructions (LLOCK and SCOND). Therefore, the assembly version
of atomic functions cannot be used. This adds pure C version of
these atomic functions.

Change-Id: Ic64dd31b0367b6dcf3a46f41c0c7ac2c2ce5eb8d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:16 -05:00
Benjamin Walsh 1831900cd3 arc: add nanokernel tickless idle support
Modified interrupt handling and idle code to enter and exit tickless
idle mode.

Change-Id: I3461ab6dba30003a4317027fc50a3ba07e830015
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:13 -05:00
Andrew Boie 377f616b3c arc: fix alignment of IRQ vector table
On ARC the IRQ and exception vectors are just one big array of
function pointers placed at the very beginning of the binary in ROM.
Vectors 0-15 are for CPU exceptions, 16-255 for interrupts.

In Zephyr these have been logically split into an execption table
followed immediately by the IRQ table, specified in the ARC linker.cmd.
However, the exception vector table defined in Zephyr had only 14
entries so the IRQ table was misaligned by 8 bytes. This went undetected
for some time as in the default configuration every entry in the IRQ
table pointed to the common demux function _isr_enter().

This patch correctly ensures that the IRQ table begins at address
0x40000040 instead of 0x40000038 like it had been.

Change-Id: I3b548df0dcabeb9d986ecd6a41e593bd02e3bd73
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Benjamin Walsh 3181df6db4 kernel: add per-thread errno support
Saves an errno per-thread, retrieved via _get_errno(), instead of
changing the value of a global variable during context switches to avoid
a hit to the context switch performance.

Per-arch asm implementations are provided for maximum performance.

Enabled by default, but can be disabled via the CONFIG_ERRNO option.

Change-Id: I81d57a2e318c94c68eee913ae0d4ca3a3609c7a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:58 -05:00
Anas Nashif 275ca60b08 Fixed file description and applied doxygen style
Removed old style file description and documnetation and apply
doxygen synatx.

Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:58 -05:00
Andrew Boie 2ec374a8df irq_offload: ARC implementation
Uses the "trap_s" exception to simulate entry into IRQ context;
offloaded functions run on the FIRQ stack.

Change-Id: I310ce42b45aca5dabd1d27e486645d23fa0b118f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif fe29e34369 arc: remove defaults and fixed typo k->K in linker.cmd file
The defauls set in architecture Kconfig are not being overwritten
by the platform, so remove those and rely on platform provided
data.

Change-Id: Ia71d9d14dddce94c29b9ca957b4ed3ae8838d96c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Dmitriy Korovkin f1420515a7 irq: Add flags to IRQ_CONNECT_STATIC() macro and irq_connect() function
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.

The change in API means that device drivers and sample
applications need to use the new API.

IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()

Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:44 -05:00
Andrew Boie 8397dc5028 _irq_handler_set: don't require old function as parameter
This was kept around since it used to be necessary for x86, and we
want our APIs to keep partity across arches, but with the x86 IRQ
refactoring this is no longer needed.

Change-Id: Iacd61f4c4d3cc33b4a15bfa083e106ba6d5da942
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:41 -05:00
Dan Kalowsky 2a63743192 cleanup: removing NOMANUAL
The \NOMANUAL tag is a remnant from days of yore and is no longer
needed or useful.  Cleaning up the code references to this.

Change-Id: I1b8cc9c9560d1dbb711f05fa63fd23386789875c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:35 -05:00
Anas Nashif 280452061d doxygen: use @a on parameters instead of < >
Change-Id: I2933df165a3c1f95b1d02f57f38bc7587008ce5d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:35 -05:00
Anas Nashif a5c3644bca arc: replaced wrong config variable
Change-Id: Ib72e35105e575dc5744fe59fd27265e6ed203daf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:35 -05:00
Dan Kalowsky da67b29569 checkpatch: warning - block_comment_style
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky 3a109b1f00 Adding in doxygen comment headers
Moving many of the functions from the old format of inline comments to
the newer doxygen format.

Change-Id: Ib0fe0d8627d7cd90219385a3ab627da8f9637d98
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky 39063598db checkpatch: error - spacing
Change-Id: Ie6e1c43581dd4b0734625b3a4e59a4ca79619e99
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:31 -05:00
Javier B Perez Hernandez f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Anas Nashif 66b55a3f7c arc: if printk is disabled, do not set variables
if printk is disabled, the variables will be unused and we will
get compiler warning.

Change-Id: I5dad791ae89d7a8c98f9e4660da472ef0caacc92
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:16:17 -05:00
Anas Nashif fc3f76d751 arc: move source files to core/
Change-Id: Ic30b2579098a54ff7ab777d9d167ab58bf08ad93
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:58 -05:00
Anas Nashif e81942e538 arc: do not include arch/cpu.h, nanokernel.h has it
Change-Id: Ic8537168211292fcedcb9c1d283d638029473932
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:36 -05:00
Benjamin Walsh e80d06deed arch: rename context.c files to thread.
Also for ARC, rename context_wrapper.S to thread_entry_wrapper.S.

Change-Id: I83318ae352a688996f8436cf3252f6108ec23dc5
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh 0dcad8331b clarify use of term 'context'
The term 'context' is vague and overloaded. Its usage for 'an execution
context' is now referred as such, in both comments and some APIs' names.
When the execution context can only be a fiber or a task (i.e. not an
ISR), it is referred to as a 'thread', again in comments and everywhere
in the code.

APIs that had their names changed:

  - nano_context_id_t is now nano_thread_id_t
  - context_self_get() is now sys_thread_self_get()
  - context_type_get() is now sys_execution_context_type_get()
  - context_custom_data_set/get() are now
    sys_thread_custom_data_set/get()

The 'context' prefix namespace does not have to be reserved by the
kernel anymore.

The Context Control Structure (CCS) data structure is now the Thread
Control Structure (TCS):

  - struct ccs is now struct tcs
  - tCCS is now tTCS

Change-Id: I7526a76c5b01e7c86333078e2d2e77c9feef5364
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Juan Manuel Cruz 044bfc60c5 build: INIT_STACKS memset fix.
This commit fixes an issue with INIT_STACKS configuration option.
k_memset is substituted by the libc memset routine to initialize a
block of memory.

Change-Id: Ic3e286d0976f618110b2828f6da76417b868aef0
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:15:26 -05:00
Benjamin Walsh 910970ed0f ffs: remove non-inline find_[first|last]_set()
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.

Change-Id: Iee2e6adcfb5da1fe0a978a05aa854e10ae82a8b8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:25 -05:00
Benjamin Walsh 2c5086cc65 irq: remove non-inline irq_lock/unlock
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.

Change-Id: I7314b96c42835f15df4c537ec11ab7961d4ee60f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Benjamin Walsh 6469e578cb irq: do not use _inline versions of irq_lock/unlock
Standardize on using the irq_lock/irq_unlock (non-inline) symbols
everywhere.

The non-inline versions provide absolutely no benefits, so they will be
removed in a subsequent commit, and the inline versions will have their
_inline suffix removed.

Change-Id: Ib0b55f450447366468723e065a60adbadf7067a9
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Benjamin Walsh c1f9fd888d irq: make utility functions private
irq_handler_set, irq_priority_set and irq_disconnect have been made
private by prepending an underscore to their names:

	irq_handler_set -> irq_handler_set
	irq_priority_set -> irq_priority_set
	irq_disconnect -> irq_disconnect

The prototypes have been removed from header files when possible, and
extern statements used in C code where they were called.

_irq_priority_set() for ARM is still in the header file because
IRQ_CONFIG() relies on it.

Change-Id: I2ad585f8156ff80250f6d9eeca4a249a4477fd9d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Andrew Boie 91156d9c7a arc: standardize ffs function names to match other arches
Change-Id: I4f384960f4c6698ef98ecf3941c30f849832135e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:15:20 -05:00
Benjamin Walsh add6b9794b arc: fixes in context switch explanation comments
There were some typos and some weird phrasing.

Change-Id: I7b183755058e5ffedca97d434c43f448aafd1926
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis 4a36991e66 arch/arc: Move fatal_error.c into 'core'
One of many steps in the transform BSPs to platforms work item.  At the end
of this work item, there should not be any code in the 'arch/arc' directory.

Change-Id: If72a6a858eb4b0f1521191fca441bed4acc6d8ce
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:37 -05:00
Anas Nashif f367f071b6 doxygen: add @brief and capitalize
Remove function name from comment and add @brief instead.
Also capitilize first letter.

Change-Id: Ib708b49bf02e5bc89b0066637a55874e659637e0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:33 -05:00
Anas Nashif 1362e3c162 doxygen: RETURNS: -> @return
Previous comment style used RETRURNS:, use @return to comply
with javadoc style.

Change-Id: Ib1dffd92da1d97d60063ec5309b08049828f6661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Anas Nashif ea0d0b220c doxygen: change comment style to match javadoc
The change replaces multiple asterisks to ** at
the beginning of comments and adds a space before
the asterisks at the beginning of lines.

Change-Id: I7656bde3bf4d9a31e38941e43b580520432dabc1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Anas Nashif cfb9332c30 arc: add missing Kconfig/Makefiles to architecture
Change-Id: I99e96853e5ddc9eb0dd9ca9711921d5b57448db7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Allan Stephens 22364188a4 Rename nanokernel's offsets/common.h to nano_offsets.h
Eliminates unnecessary "offsets" subdirectory, and aligns file
name with gen_offset.h which resides in the same directory.

Change-Id: I8cea3bc54b5ceae3091d4a5c77c59ab826339f75
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens e8f50f5717 Rename nanokernel's genOffset.h to gen_offset.h
Eliminates use of non-standard camelCase file name.

Change-Id: I809de5f72b40adfd49cbc128992de934e3ec66e3
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens c29d41cab7 Rename nanokernel's nanok.h to nano_private.h
The new name better reflects that this file contains all private
nanokernel APIs that are used by various kernel subsystems.

Change-Id: I4c258d582e93753eec9e575fdb5f9f2109417a0f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Benjamin Walsh 2672025969 nanokernel: add and initialize timeout fields in ccs/s_NANO
s_NANO contains the timeout queue, and each ccs needs a struct
_nano_timeout object that gets linked in the nanokernel timeout queue.

Change-Id: Iad027eaaebcffe190e95f0b9d068f047062559c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:14:22 -05:00
Benjamin Walsh f9d34ff899 nanokernel: rename struct s_CCS to struct ccs
Follow coding conventions.

Change-Id: Ie398d66e6255b76b4546aa9c827997b5dfb0743c
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:14:22 -05:00