Setting the number of memory wait cycles must take place while the clock
is set to 32MHz or less. This patch ensure the MEMWAIT register is
changed before the clock is changed from its default value (of 8MHz).
Note that in order to set MEMWAIT to 1 the power control mode must be
set to high speed (which is why the lines of code interacting with the
OPCCR register have also been moved).
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Due to a typo it is not possible to select the sub-clock oscillator
(SOSC) as a clock source for an RA Microcontroller. This patch resolves
the issue.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Yong Cong Sin