OrgZephyr/zephyr
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zephyr
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2 Commits

Author SHA1 Message Date
Maureen Helm 15baad9419 soc: riscv32: Move rv32m1 flash memory definitions to dts 
Moves the flash memory definitions from Kconfig to device tree for the
rv32m1 ri5cy and zero-riscy cores.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
 2019-05-06 19:09:59 -04:00
Maureen Helm 948ef47cf4 dts: riscv32: Add rv32m1 zero-riscy core support 
Refactors peripheral addresses, clocks, and compatibles from the ri5cy
core dtsi into a common soc dtsi, then attaches interrupts in
core-specific dtsi files.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
 2019-05-06 14:52:17 -05:00