The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.
The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.
The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.
The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.
Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Quark SE provides various clock controllers through its SCSS block.
Peripheral, external, sensor, and others.
This current drivers provides only the clock gating capability, for
peripheral, external and sensor. But it could support divider and more
other features once defined in the generic API.
Note: such clock has _nothing_ to do with a Real Time Clock (RTC).
An RTC provide clock timing like a watch would do. Here the clock
controller is about circuit clocking.
Change-Id: I1a365ae730dfc6be7686271f7fbb693e64a6ff6f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Maciek Borzecki