Commit Graph

36 Commits

Author SHA1 Message Date
Anas Nashif 689ea54b78 tests: do not filter on SMP, use board yaml file
Avoid expensive runtime filtering and use platform features instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-05-24 07:50:50 -04:00
Fabio Baltieri 3e7e44b70d yamllint: indentation: fix files in boards/
Fix the YAML files indentation for files in boards/.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-04 14:23:53 +01:00
Kumar Gala 81d904554a boards: Change defconfigs to use CONFIG_MP_MAX_NUM_CPUS
Move to using CONFIG_MP_MAX_NUM_CPUS in defconfig as we phase
out CONFIG_MP_NUM_CPUS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-19 16:01:20 +02:00
Nicolas Pitre 9ac6779b2d riscv: smp: update the qemu_riscv32/64 configs
No usermode nor stackguard CI tests are performed if CONFIG_RISCV_PMP
is not set.

In turn, this requires a larger privileged stack on RV64 just like
the non SMP case.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-09-28 07:53:56 +00:00
Kumar Gala 390464ce3b timers: remove defconfig setting of timer drivers
Now that timer drivers are enabled based on devicetree we can
remove any cases of them getting enabled by *_defconfig files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Kumar Gala 1a75e77b6b intc: remove defconfig setting of interrupt controller drivers
Now that interrupt controller drivers are enabled based on devicetree
we can remove any cases of them getting enabled by *.conf files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-01 10:25:36 +02:00
Carlo Caione 5fece03d7d riscv: Introduce Zicsr and Zifencei extensions
And enable the new extensions on all the SoCs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-08-29 16:57:18 +02:00
Gerard Marull-Paretas 1416c8ce12 boards: qemu: delete all QEMU logos
We had a bunch of QEMU logos embedded in all QEMU boards. Logos do not
add much value to the documentation, so just delete them.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-29 10:18:18 +02:00
Kumar Gala 79cf938378 boards: riscv: Remove label property from devicetree
The label property isn't needed in devicetree so remove it.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-04 13:47:02 +02:00
Kumar Gala 10329165be serial: remove defconfig/proj setting of serial drivers
Now that serial drivers are enabled based on devicetree we can remove
any cases of them getting enabled by *defconfig and proj.conf files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 09:29:24 -05:00
Kumar Gala 1c1c57b31b gpio: remove defconfig/proj setting of GPIO drivers
Now that gpio drivers are enabled based on devicetree we can remove
any cases of them getting enabled by *defconfig and proj.conf files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 08:49:38 +02:00
Carlo Caione 10061efdc4 riscv: Rework and cleanup Kconfig
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-05 14:28:42 +02:00
Maureen Helm 7a9703f9a8 dts: riscv: sifive: Move SoC devicetree includes under a vendor dir
Cleans up SoC devicetree include file locations to follow the convention
of dts/<arch>/<vendor>/

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-05-09 17:54:48 -04:00
Gerard Marull-Paretas db508379c2 boards: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all boards code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:15 +02:00
Keith Packard c33ce95277 boards/riscv: Enable THREAD_LOCAL_STORAGE by default on qemu_riscv32
This provides more test coverage than is offered by the TLS-specific
tests.

Signed-off-by: Keith Packard <keithp@keithp.com>
2022-04-28 11:09:01 +09:00
Shawn Nematbakhsh c74526919d soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.

This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
Filip Kokosinski 38f38e0be8 boards: FE310-based boards: transition to pinctrl driver
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Filip Kokosinski a9543e0ff4 boards: qemu_riscv32: add pinctrl configuration for qemu_riscv32_xip
Add pinctrl configuration for future use with the new pinctrl driver.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Ederson de Souza 6babbd32e1 boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp
Based on qemu_riscv32 and qemu_riscv64, add minimal SMP support
using the "virt" machine.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-02-25 19:13:50 -05:00
Jim Shu 74faa18902 soc: riscv: virt: enable RISC-V PMP support
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Filip Kokosinski 94428044e2 cmake: support multiple entries in board.cmake
Currently there is no way to support running a board on multiple
emulation platforms nor to choose a desired emulation platform for the
simulation to be run on. This commit introduces a new
SUPPORTED_EMU_PLATFORMS list, which defines available emulation
platforms for a given board.

Fixes #12375.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-11-12 21:33:42 -05:00
Anas Nashif b3abe11104 boards: remove CONFIG_PRINTK from board _defconfig
We should not enable this config in the board, this is an
application config.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-10-18 09:49:45 -04:00
Jim Shu 81b0bdfa99 board: riscv: add qemu_riscv32_xip board to test XIP mode
Add a variant riscv build target that only is run for tests tagged
with "xip".

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-04-16 12:26:10 +02:00
Anas Nashif ff24090527 tests: filter default platforms
Do not attempt to build/run all tests. Emulation platforms should
primarily build kernel and architecture related tests.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-02-19 14:41:01 -05:00
Martin Åberg 8a2d5aa716 boards: qemu_riscv32 use virt machine
Upgrade board specification to use the VirtIO board.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Martin Åberg d2e9568543 riscv: make COMPRESSED_ISA independent of FLOAT_HARD
The CONFIG_FLOAT_HARD config previously enabled the C (compressed)
ISA extensions (CONFIG_COMPRESSED_ISA). This commit removes that
dependency.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Andrew Boie a9670ab5cf boards: centralize QEMU icount management
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-24 20:28:36 -04:00
Wentong Wu 589a0c22ff boards: qemu_riscv32: enable icount mode
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Corey Wharton d873573f76 tests: fp_sharing: Enable build-only tests for RISC-V QEMU platform
Enables build-only tests for the qemu_riscv32 platform.

Signed-off-by: Corey Wharton <coreyw7@fb.com>
2020-04-22 16:39:48 -07:00
Ulf Magnusson c5839f834b kconfig: Remove assignments to CONFIG_<arch> syms and hide them
All board defconfig files currently set the architecture in addition to
the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up
defconfig files.

CONFIG_<arch> symbols currently being set in configuration files also
means that they are configurable (can be changed in menuconfig and in
configuration files), even though changing the architecture won't work,
since other things get set from -DBOARD=<board>. Many boards also allow
changing the architecture symbols independently from the SoC symbols,
which doesn't make sense.

Get rid of all assignments to CONFIG_<arch> symbols and clean up the
relationships between symbols and the configuration interface, like
this:

1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and
   turn the CONFIG_<arch> symbols into invisible
   (promptless/nonconfigurable) symbols instead.

   Getting rid of the choice allows the symbols to be 'select'ed (choice
   symbols don't support 'select').

2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols.
   This makes sense since you know the architecture if you know the SoC.

   Put the select on the SOC_* symbol instead for boards that don't have
   a SOC_SERIES_*.

3. Remove all assignments to CONFIG_<arch> symbols. The assignments
   would generate errors now, since the symbols are promptless.

The change was done by grepping for assignments to CONFIG_<arch>
symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the
same defconfig file, and putting a 'select' on it instead.

See
https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed
for a split-up version of this commit, which will make it easier to see
how stuff was done. This needs to go in as one commit though.

This change is safer than it might seem re. outstanding PRs, because any
assignment to CONFIG_<arch> symbols generates an error now, making
outdated stuff easy to catch.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-08 00:50:08 -06:00
Kumar Gala 1dc4b1dd2f boards: shrink image sizes
Reduce images sizes of boards.  Get a roughly 3x reduction in size.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-02-07 13:52:45 -05:00
Peter A. Bigot f83ad78261 dts: jedec,spi-nor: require size property
The SPI NOR driver requires that the size (in bits) be provided in the
devicetree node.  Update the binding to make the property required,
and update all nodes based on the memory chip identified.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2019-11-09 15:26:06 +01:00
Ulf Magnusson 975de21858 kconfig: Global whitespace/consistency cleanup
Clean up space errors and use a consistent style throughout the Kconfig
files. This makes reading the Kconfig files more distraction-free, helps
with grepping, and encourages the same style getting copied around
everywhere (meaning another pass hopefully won't be needed).

Go for the most common style:

 - Indent properties with a single tab, including for choices.

   Properties on choices work exactly the same syntactically as
   properties on symbols, so not sure how the no-indentation thing
   happened.

 - Indent help texts with a tab followed by two spaces

 - Put a space between 'config' and the symbol name, not a tab. This
   also helps when grepping for definitions.

 - Do '# A comment' instead of '#A comment'

I tweaked Kconfiglib a bit to find most of the stuff.

Some help texts were reflowed to 79 columns with 'gq' in Vim as well,
though not all, because I was afraid I'd accidentally mess up
formatting.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 15:53:23 +01:00
David B. Kinder 60136f00cb doc: add how to exit from QEMU in samples
While trying out the hello_world sample built for QEMU, I was expecting
the sample app to exit and I'd return to a command prompt.  Nope.  You
need to exit QEMU manually, so add that step to the sample instructions.
Looking around, there are more uses of QEMU like this that could use
this added step after running the sample app.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-09-02 12:06:08 -04:00
Nicolas Pitre 75bf3c5368 riscv: freedom: rename RISCV32 to RISCV
This code is common to 32- and 64-bit builds.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-08 00:29:24 -04:00
Nicolas Pitre 1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00