PCI enumeration modifies pci_dev and port at driver initialization,
these objects move from config_info to driver_data in preparation for
config_info becoming const.
This driver shares a unified uart configuration structure with other
uart device drivers. The structure uses 'union' and the preprocessor
to customize the structure to the drivers specific requirement. There
appears to be no compelling reason why all the uart drivers should
share the same (customized) config_info structure. In order to
re-organize the structure for this driver to get config_info const, an
ns16550 specific config structure is defined and the driver switched
over from the generic uart_config.
Change-Id: I31932d811f623a9370b69903114ae97b15d65886
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I0257e242a2d3bc4e353a3477364a4d9a7fb72b82
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The drivers config structure initializer sets sys_clk_freq statically.
The runtime repeated setup of sys_clk_freq is superfluous, and
inconsitent with const driver config structures.
Change-Id: I115e2b70b193b567de83132f3984e48b2dded0a2
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I8ecc10b50e23d2dbe987e3318bac09e235b1e1da
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
Updated CONFIG_SOC_QUARK_SE_SS to CONFIG_SOC_QUARK_SE_C1000_SS
Change-Id: I7dc02d91a4d739f6cd3f84001d1dd29759317163
Signed-off-by: Javier B Perez <javier.b.perez.hernandez@intel.com>
Update the power sample and drivers with the new device driver power
management API using the existing logic
Jira: ZEP-954
Change-Id: Idd94232e458767635973e94e9fc673c01612c1e2
Signed-off-by: Amir Kaplan <amir.kaplan@intel.com>
The Sensor Subsystem has different IRQ numbers for the same device
across CPUs. QMSI declares these, but doesn't do anything to try to
map it automatically, so we have to do it in the driver.
Similarly the SCSS interrupt routing (the SoC-wide "APIC", which is
distinct from the per-CPU interrupt masking hardware) needs to know
which CPU we're trying to unmask an interrupt for.
Change-Id: I27e5ec44f324f869e16a92e7ef40a22a305d98a2
Jira: ZEP-546
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
One remaining reference to uart_qmsi_pm_save_config
was missed by patch bc60506d3e.
This reference is removed.
This fixes the following error:
...
drivers/built-in.o: In function `uart_qmsi_line_ctrl_set':
/drivers/serial/uart_qmsi.c:439:
undefined reference to `uart_qmsi_pm_save_config'
collect2: error: ld returned 1 exit status
...
Change-Id: I1ceda0e152db5a1c7f70d67c04b931416687031a
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
In order to restore uart context after entering
SYS_PM_DEEP_SLEEP, suspend and resume functions
are called.
The following parameters are restored:
- All registers for the UART device.
- UART clocks.
The FIFO control register cannot be read back and is
not stored in the device configuration.
The default parameters are applied for them.
The suspend/resume functionality is implemented in
the QMSI shim layer as a fast and temporary solution,
it will be removed and migrated to QMSI later.
Change-Id: I4be9246f6aa5a6e0d91df54c1c69574060136607
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
CONFIG_UART_INTERRUPT_DRIVE should be CONFIG_UART_INTERRUPT_DRIVEN
CONFIG_UART_LINE_CTR should be CONFIG_UART_LINE_CTRL
Change-Id: I11fba5b387e3d36711cd3c813fc8a297ae23af05
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The macro defining the device_pm_ops structs is located inside an
ifdef for CONFIG_UART_QMSI_0, so when the UART_0 is disabled at build
time, but UART_1 is still used, it references a struct not defined.
Fix it by placing the DEFINE_DEVICE_PM_OPS line outside the ifdef block.
Change-Id: I7dafda162741201ee47b5b480c07ec8c1f373d64
Signed-off-by: Iván Briano <ivan.briano@intel.com>
This adds some basic suspend/resume support in the uart_qmsi
driver. This is part of a change to enable device suspend/resume
and deep sleep support in sample PM application.
Jira: ZEP-512
Change-Id: I38cfbfb352d0027b7beaadebedbc10002dade50a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Use IOAPIC_EDGE instead of IOAPIC_LEVEL to fix missing interrupts.
During tests it was found that using IOAPIC_LEVEL interrupts for UART at
some points are lost.
Proposed by Calando, Antoine <antoine.calando@intel.com>
Change-Id: I18b20217c4d73fdeaa424bf59d00f6be1ec6ef1b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Revert patch fixing Bluetooth application with Debug enabled crashing.
This reverts commit 029d3beb57.
Change-Id: I0004dae656ca5a0b44da9f12542088d47c38b837
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
QMSI uart driver has removed qm_uart_get_config API. Updated
the shim driver to use alternatives.
Change-Id: I3ccfd0dfec3711d250de7d1004275d9b02d7477a
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
Global data and device setting can be messed up by concurrent
API calls. This change is to serialize the access.
Jira: ZEP-454
Change-Id: I520722aecab7db443d053fd45498a22e165889de
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This currently only supports outgoing messages without interrupts.
Change-Id: I635562f47106eb6cdc7104a8160e431bebea25dc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In order to change the baudrate the DLAB bit of the LCR register has to
be set to 1 (This bit is used to enable reading and writing of the
divisor latch register). This bit must be cleared after the baudrate
setup in order to access other registers.
The set_baud_rate function correctly sets the DLAB bit of the LCR reg but
never clears it. Therefore the ns16550 doesn't properly work any more
after updating the initial baud rate.
In order to fix this issue the LCR reg has to be temporary saved
(because it contains other important settings). After switching to a new
baud rate the LCR reg value has to be restored.
Change-Id: Ied4db683cbf40ba3125e747552968ddf1a66e2be
Signed-off-by: Jeremie GARCIA <jeremie.garcia@intel.com>
Signed-off-by: Sebastien GRIFFOUL <sebastien.griffoul@intel.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On current Curie-based boards UART 0 is wired to the nRF51 BLE
controller and requires HW flow control to be enabled in order to
function. This patch restores the same behavior that was present
before the "qmsi: uart: use built-in qmsi driver" patch.
Change-Id: If7ea347f5ab8b460f39123dcc0d75d711a5a1c2a
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use SOC_SERIES_* for naming SoCs with similar features and architectures
with the goal of code reuse. The Series in the config variable should avoid
name collisions and clearly denote the relationships within an SoC family.
Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use CONFIG_SOC_FAMILY for the top level SoC family. A family
will have different SoCs or different SoC series with multiple
SoCs.
Adding the Family string to the config variable to avoid confusion
between actual SoCs and families and to prevent name collisions.
Change-Id: Ic99a2c1df7850dee3a45641027af82464dd6fadb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Note that the failure case can only be reached when PCI is enabled.
Otherwise, the if-block is always false, which reduces code size
for non-PCI platforms.
Change-Id: Ib98b78a75cc2a5f124e67f32f2bf82960a963aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IRQ triggering condition should be specified by SoC as it is
a decision for hardware design. This should not be configurable
in kconfig.
The default is to be triggered on rising edge, just as the same
old kconfig did.
Change-Id: If59d88a30711eb8e03d9cc4f409055cefe1995c5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves those kconfig options which should be declared in
SoC or board header files instead. These are the one
that are tied to SoC or board and there is no need
for them to be configurable in kconfig.
Change-Id: I243d634f1a4a11dc8dc3530d95f93371015492b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.
Change-Id: Ia252958d205e0100d1b92e2a12d4c22411bc94b9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.
Change-Id: I79b142414143bc5ef585d3136a00375233de1723
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The patch extends STM32 serial port driver with support for IRQ API of
the common UART port driver API.
Change-Id: If105e8528ea4ed4181cc4af0c97c24aa874e69e0
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add driver for U(S)ART ports on STM32 MCUs. The driver implements basic
RX/TX functionality. Data transmission is implemented using polling. The
driver configures the port to use 8bit data transmission, 1 stop bit, no
parity control.
The driver exposes a public uart driver API and registers a single UART
device 'UART_0'. The device binds to USART1 peripheral and performs
required pinmux and clock control configuration. The device can be
initialized at the PRIMARY level, with default device priority.
The driver has been verified to work with a sample Hello World
application on a STM32F103 series MCU.
Change-Id: Iae103fcd8d2fb0a6c173cf141a68e17791255aab
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Marcus Shawcroft