Adds:
* PP and Read 4-Byte command defines
* PP 1-1-2 define
* Missing 1-2-2 (0xBB) and Read Fast (0x0B) command defines
Re-arranges the commands so that they stay in order.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Renames 4PP define to PP_1_4_4
* Adds PP_1_1_4 define
That matches linux kernel defines a bit more.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
With the introduction of the OSPI NOR flash controller
more octal commands and parameters are defined.
It completes the existing SPI commands
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for S2B1 quad-enable-requirements.
Add wrsr call for various QER modes
S2B1v6 mode tested with Winbond W25Q128JV series and pp4o and read4io
commands.
Signed-off-by: Zack Cornelius <zcornelius@securityesys.com>
This change provides support for 4 IO read (via 4READ command) and
program (via 4PP). Flash memory pins SIO[0123], CLK and CS are used.
All of them are controlled by stm32 QSPI IP block.
The instruction code for fast reading as well as number of latency
cycles required are read from SFDP structure provided by flash memory.
The number of required read latency cycles when performing reading
is the sum of SPI-NOR memory mode bits and wait states (also named
as 'dummy cycles').
It also has been assumed that memory, which supports fast read (4READ),
also will support fast programming (4PP command) as this information is
not available in SFDP.
One also need to enable the QUAD IO support in board's device tree by
defining 'spi-bus-width = <4>' property. It is required as it may
happen that not all QSPI dedicated pins are used (for example only two
of them are available).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
For proper operation of QUADSPI IP block, both sides of communication;
NOR flash memory and STM32 controller need to support 4 IO
transmission.
After this change the QSPI stm32 driver is able to program NOR flash
memory to switch itself to use all 4 IO lines (SIO[0123]) to transmit
and receive data.
The QE bit (in SPI-NOR's Status Register) is the non-volatile one, so
setting it is done only once (at first boot of the device).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit provides define for reading the control register (CR) on
the flash memory.
In that register the information about 4B addressing is stored.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Use the new SFDP infrastructure to read the supported erase type sizes
and commands from the Basic Flash Parameters block. This removes the
need for explicit reference to most block sizes from this driver.
We're also seeing devices where the page size is not 256 bytes.
Accommodate them.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add internal API to enter and exit deep power-down mode. Add Kconfig
option to return to DPD whenever device is not active.
When device power management becomes more mature it should be possible
to implement it, which would allow use of DPD without having to enter
and exit DPD between consecutive transactions.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The JEDEC API defines the hardware page, sector, and block sizes.
Deprecate the Kconfig settings, remove the `erase-size-block` property,
and add `has-be32k` to indicate that 32K-byte erase is supported.
Rework the driver to use the constants instead of configured values.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Configuration of Erase command is specified in DTS. Hence
the corresponding changes in Kconfig are removed.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This driver is inspired from the w25qxxdv SPI NOR flash driver which was
already implementing the CFI (Common Flash Interface) for its purpose.
To handle other NOR flash a flash id table (as Linux do) which contains
the geometry for a few SPI NOR flash based on their JEDEC ID has been
introduced.
We currently support the following flash:
- W25Q80
- W25Q16
- W25Q32
- S25FL216K
- MX25UM512
The read and write functions are able to handle more then one page at a
time and return the number of bytes read or write.
Also because every NOR flash expect to disable the write protection
before writing or erasing, the write enable command is now part of the
write and erase functions.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Georgij Cernysiov