Commit Graph

8 Commits

Author SHA1 Message Date
Flavio Ceolin 46715faa5c kernel: Remove _IntLibInit function
There were many platforms where this function was doing nothing. Just
merging its functionality with _PrepC function.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-28 14:59:10 -08:00
Adithya Baglody e9cb0ae72a arch: kernel_arch_func.h: Fix MISRA violation
Always compare unsigned interger type with another unsigned
integer type. Currently in nios2, posix, riscv32, x86 and xtensa
we were comparing the _kernel.nested variable with a signed
interger type. Fixed this violation.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-10-17 12:17:58 -04:00
Flavio Ceolin 67ca176754 headers: Fix headers across the project
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Andrew Boie 507852a4ad kernel: introduce opaque data type for stacks
Historically, stacks were just character buffers and could be treated
as such if the user wanted to look inside the stack data, and also
declared as an array of the desired stack size.

This is no longer the case. Certain architectures will create a memory
region much larger to account for MPU/MMU guard pages. Unfortunately,
the kernel interfaces treat both the declared stack, and the valid
stack buffer within it as the same char * data type, even though these
absolutely cannot be used interchangeably.

We introduce an opaque k_thread_stack_t which gets instantiated by
K_THREAD_STACK_DECLARE(), this is no longer treated by the compiler
as a character pointer, even though it really is.

To access the real stack buffer within, the result of
K_THREAD_STACK_BUFFER() can be used, which will return a char * type.

This should catch a bunch of programming mistakes at build time:

- Declaring a character array outside of K_THREAD_STACK_DECLARE() and
  passing it to K_THREAD_CREATE
- Directly examining the stack created by K_THREAD_STACK_DECLARE()
  which is not actually the memory desired and may trigger a CPU
  exception

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-01 16:43:15 -07:00
Anas Nashif 8df439b40b kernel: rename nanoArchInit->kernel_arch_init
Change-Id: I094665e583f506cc71185cb6b8630046b2d4b2f8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-19 10:59:35 -05:00
Anas Nashif b84dc2e124 kernel: remove all remaining references to nanokernel
Change-Id: I43067508898bc092879f7fe9d656ccca6fd92ab2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:10 +00:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Jean-Paul Etienne cd83e85edc arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.

1) exceptions/interrupts/faults are handled at the architecture
   level via the __irq_wrapper handler. Context saving/restoring
   of registers can be handled at both architecture and SOC levels.
   If SOC-specific registers need to be saved, SOC level needs to
   provide __soc_save_context and __soc_restore_context functions
   that shall be accounted by the architecture level, when
   corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.

2) As RISC-V architecture does not provide a clear ISA specification
   about interrupt handling, each RISC-V SOC handles it in its own
   way. Hence, at the architecture level, the __irq_wrapper handler
   expects the following functions to be provided by the SOC level:
   __soc_is_irq: to check if the exception is the result of an
                 interrupt or not.
   __soc_handle_irq: handle pending IRQ at SOC level (ex: clear
                     pending IRQ in SOC-specific IRQ register)

3) Thread/task scheduling, as well as IRQ offloading are handled via
   the RISC-V system call ("ecall"), which is also handled via the
   __irq_wrapper handler. The _Swap asm function just calls "ecall"
   to generate an exception.

4) As there is no conventional way of handling CPU power save in
   RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
   functions just unlock interrupts and return to the caller, without
   issuing any CPU power saving instruction. Nonetheless, to allow
   SOC-level to implement proper CPU power save, nano_cpu_idle and
   nano_cpu_atomic_idle functions are defined as __weak
   at the architecture level.

Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:52:23 +00:00