Add a small paragraph about Floating Point services
in Cortex-M, focusing on the important considerations
around footprint and runtime overhead.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add a small section about specific considerations
around chain loadable images.
Add a brief section about code relocation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Memory protection features in Cortex-M applications
- user mode and system calls
- MPU based stack overflow detection
Add section about memory map and mpu programming.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
- add a paragraph about CMSIS
- add a note about maintenance status of Cortex-M
- add a paragraph about testing the Cortex-m porting
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add list of the available QEMU targets for Cortex-M
platforms in Zephyr along with the corresponding feature set.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding sections to describe
- isr handling principles
- different kinds of interrupts
- reserved interrupts and levels
- locking and unlocking interrupts
- zero latency interrupts
- dynamic direct interrupts
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding a small paragraph to describe the details around
thread stack alignment. Adding a detailed section to cover
the thread context-switch and the stack limit checking.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
ARM Cortex-M user guide. Initial commit including a table
for listing supported features in the different
Cortex-M variants.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
List of the changes:
* update info about ARCv3 HS6x which support has been upstreamed
recently
* mark HS3x userspace support as Y
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
There was a restriction that KERNEL_VM_OFFSET must equal to
SRAM_OFFSET so that page directory pointer (PDP) or page
directory (PD) can be reused. This is not very practical in
real world due to various hardware designs, especially those
where SRAM is not aligned to PDP or PD. So rework those bits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the bits to the gen_mmu.py script so that extra mappings
can be added with caching disabled. This is useful for mapping
MMIO regions where caching is not desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds to page on the x86 virtual memory about how to specify
extra page table mappings during build.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
As of today, Zephyr misses any kind of info page with overall
support status of ARC processors, their HW features and SW tools.
Fix that.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Ioannis Glaropoulos