Commit Graph

29 Commits

Author SHA1 Message Date
Anas Nashif cb888e6805 kernel: remove nano/micro wording and usage
Also remove some old cflags referencing directories that do not exist
anymore.
Also replace references to legacy APIs in doxygen documentation of
various functions.

Change-Id: I8fce3d1fe0f4defc44e6eb0ae09a4863e33a39db
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:03 +00:00
Benjamin Walsh f6ca7de09c kernel/arch: consolidate tTCS and TNANO definitions
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.

Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.

The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.

The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.

Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.

Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-12 07:04:52 -05:00
Anas Nashif 7cac3b9625 arch: arc: arm: sys_thread_self_get -> k_current_get
Change-Id: Iaa01b0d8733d76888524cfd258bacbd9c11142de
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-10 18:52:51 +00:00
Andrew Boie 757dae5b7d x86: introduce new segmentation.h header
This header has a bunch of data structure definitions and macros useful
for manipulating segment descriptors on X86. The old IDT_ENTRY defintion
is removed in favor of the new 'struct segment_descriptor' which can be
used for all segment descriptor types and not just IRQ gates.

We also add some inline helper functions for examining segment registers,
descriptor tables, and doing far jumps/calls.

Change-Id: I640879073afa9765d2a214c3fb3c3305fef94b5e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-20 20:46:45 +00:00
Andrew Boie e931410756 x86: fatal: don't report bogus interrupt vectors
_irq_controller_isr_vector_get() now returns -1 if it couldn't
determine which vector was activated.

Issue: ZEP-602
Change-Id: Ib0f5dbc3b68cc5e2c3a23121530e178aede20d06
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-08 12:48:20 -07:00
Andrew Boie e98ac235e6 x86: declare internal API for interrupt controllers
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.

Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.

Contents of the API:

- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.

- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags

- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced

- In assembly language domain, _irq_controller_eoi implements
EOI handling.

- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.

Specific changes made:

- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.

- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.

- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.

- Unused APIs removed, or folded into calling code when used just once.

- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway

Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-06 18:35:47 +00:00
Andrew Boie 0827d6c775 x86: fix incorrect printk() usage
Change-Id: I346a62f6a4611c7aaaae8b50dab17913faf4033f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-28 07:47:28 -04:00
Andrew Boie 17c0b372a2 x86: improve exception APIs
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:

 _EXCEPTION_CONNECT_CODE(handler, vector)
 _EXCEPTION_CONNECT_NOCODE(handler, vector)

For x86 exceptions that do and do not push error codes onto
the stack respectively.

In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c

Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.

CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.

Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-28 18:13:24 +00:00
Benjamin Walsh e83ddd1471 x86: add debug hook in _NanoFatalErrorHandler()
Allow a debug server such a GDB to take control when a fatal error
occurs. The debug server simply has to define a _debug_fatal_hook()
function that will override the weak function installed by default.

Change-Id: Ib9dca5755868f747b697fa3178e09109f1eedb07
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-04-16 05:29:21 +00:00
Andrew Boie 89ec552be9 x86: iamcu: fix exception NANO_ESF parameter
On SysV ABI, the NANO_ESF parameter is passed in via the stack.
For IAMCU, this is instead expected to be in EAX.

_ExcEnter is currently using EAX to stash the return address of
the calling stub while it does a stack switch. Change it to use ECX
for this purpose, and if we are running with IAMCU place the
parameter in EAX instead of pushing it.

The output of the fault handler has been cleaned up a bit and it
now also includes the code segment.

Change-Id: I466e3990a26a1a82dd486f3d8af5395eab60b049
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:16 -05:00
Andrew Boie a50f923504 x86: fatal: report vector number of spurious interrupts
Change-Id: I79de1a77d2b5f87aa3bd1a7aebd0253dbb069252
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:04 -05:00
Anas Nashif 275ca60b08 Fixed file description and applied doxygen style
Removed old style file description and documnetation and apply
doxygen synatx.

Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:58 -05:00
Andrew Boie c065ed5d78 x86: reduce footprint of exception debugging
We're smart, we can look up the vector IDs in a book if we
don't already know what they are.

Change-Id: Iaff3986d7c96dea597be4b2a5b13721ab57980fa
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis c5b10c6006 x86: Display registers on fatal error
Change-Id: Idb05fbb707f2c95173423c928acda2a07e962989
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis 6338c4518c x86: Update NANO_ESF and NANO_ISF structures
As the system always operates in ring 0, neither the SS nor ESP registers
are pushed onto the stack when an exception or an interrupt occurs.
However, as the ESP field is still relevant to debugging fatal errors, a
place has been carved for it in the NANO_ESF.

Change-Id: Ibb2578c69fa6365fd6e9dbf7b51f461063dadc68
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis e7018455d8 x86: Remove cr2 field from NANO_ESF structure
As page fault exceptions can not occur in the system as it is currently
designed, there is no need to track the CR2 register as part of the
exception stack frame.

Change-Id: I75d7a74c5d2c6efcc0e9141d2662861bc2052629
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Andrew Boie b43758d22a x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.

Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.

CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.

Some other out-of-date verbiage in comments related to supporting
non-APIC removed.

Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.

SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.

All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.

_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.

Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:41 -05:00
Dan Kalowsky 2a63743192 cleanup: removing NOMANUAL
The \NOMANUAL tag is a remnant from days of yore and is no longer
needed or useful.  Cleaning up the code references to this.

Change-Id: I1b8cc9c9560d1dbb711f05fa63fd23386789875c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:35 -05:00
Dan Kalowsky da67b29569 checkpatch: warning - block_comment_style
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky 3a109b1f00 Adding in doxygen comment headers
Moving many of the functions from the old format of inline comments to
the newer doxygen format.

Change-Id: Ib0fe0d8627d7cd90219385a3ab627da8f9637d98
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:33 -05:00
Andrew Boie be3e3b0f8c x86: Improve exception/trap debugging
Currently when an unhandled exception or trap occurs, we don't know
specifically which one happened. The CONFIG_EXCEPTION_DEBUG option
installs handlers for various exceptions and prints out details
when they happen.

Change-Id: I4d3fe4544c3e2583c4f83b306b86ac0595d9ce0e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:29 -05:00
Javier B Perez Hernandez f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Peter Mitsis 8571845c15 x86: Fix default ESF
Fixes the initialization of the default exception stack frame to ensure that
every field of the structure is initialized to the dummy value of 0xdeaddead.

Change-Id: Ic7a5b66204172b53a657c9540196f01a74e1000c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:21 -05:00
Benjamin Walsh 0dcad8331b clarify use of term 'context'
The term 'context' is vague and overloaded. Its usage for 'an execution
context' is now referred as such, in both comments and some APIs' names.
When the execution context can only be a fiber or a task (i.e. not an
ISR), it is referred to as a 'thread', again in comments and everywhere
in the code.

APIs that had their names changed:

  - nano_context_id_t is now nano_thread_id_t
  - context_self_get() is now sys_thread_self_get()
  - context_type_get() is now sys_execution_context_type_get()
  - context_custom_data_set/get() are now
    sys_thread_custom_data_set/get()

The 'context' prefix namespace does not have to be reserved by the
kernel anymore.

The Context Control Structure (CCS) data structure is now the Thread
Control Structure (TCS):

  - struct ccs is now struct tcs
  - tCCS is now tTCS

Change-Id: I7526a76c5b01e7c86333078e2d2e77c9feef5364
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Peter Mitsis ed610c5bd5 x86: Replace references to BSP with platform
Removes references to obsolete BSP terminology.  Where appropriate, replaces it
with platform terminology.

Change-Id: I41fc099844d137dd0ea87cce0f675dc6f022ad40
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:43 -05:00
Anas Nashif f367f071b6 doxygen: add @brief and capitalize
Remove function name from comment and add @brief instead.
Also capitilize first letter.

Change-Id: Ib708b49bf02e5bc89b0066637a55874e659637e0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:33 -05:00
Anas Nashif 1362e3c162 doxygen: RETURNS: -> @return
Previous comment style used RETRURNS:, use @return to comply
with javadoc style.

Change-Id: Ib1dffd92da1d97d60063ec5309b08049828f6661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Anas Nashif ea0d0b220c doxygen: change comment style to match javadoc
The change replaces multiple asterisks to ** at
the beginning of comments and adds a space before
the asterisks at the beginning of lines.

Change-Id: I7656bde3bf4d9a31e38941e43b580520432dabc1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Allan Stephens 35cf49d479 Standardize naming of nanokernel core source files for x86
Gets rid of "nano" prefix on these nanokernel files.

Change-Id: Ib87323b14779bf3673ec2826023eb94b4b7cc81e
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00