In old way, gic_rdists[cpu] is calculated via MPIDR_TO_CORE(), but in
real hardware, MPIDR_TO_CORE() isn't a value increment from 0 one by
one, and that will lead gic_rdists[cpu] to point to a wrong address.
GICv3 provides the register GICR_TYPER[1] and it has a field named
Affinity_Value. This field can help to determine where gic_rdists[cpu]
should point.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This implements support for the optional Interrupt Translation Service
(ITS) module of the GICv3 Interrupt Controller.
The current implementation is designed for MSI/MSI-X interrupt delivery
in mind.
The gicv3 driver calls each ITS INVALL command when LPI interrupts are
enabled/disabled.
A simple atomic integer is used to allocate unique LPI INTIDs to ITS
users.
CPUs numbers are directly mapped as ICIDs into the Collections Table.
As a limitation it doesn't support indirect Device table to simplify
implementation but may use a large amount of memory.
INV, DISCARD, MOVI and MOVALL commands are not implemented.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The LPI (Locality-specific Peripheral Interrupts) are edge-triggered
message-based interrupts that can use an Interrupt Translation
Service (ITS) to route an interrupt to a specific Redistributor and
connected PE.
This implement the necessary LPI support when an ITS is enabled.
The LPI states are stored in memory-backed tables.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When affinity routing is enabled for Non-secure state
( GICD_CTLR.ARE_NS is '1'), need to set routing information
for the SPI interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
In SMP, MPID is mybe not equal to cpu logic ID, so can't
use MPID to get rdist base address from gic_rdists[], this
patch get logic ID from arch_curr_cpu()->id, and
find current CPU's rdist base address from:
gic_rdists[cpu_logic_id]
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Huifeng Zhang