These need to be gpio controllers and have the necessary specifier
properties for use in gpio specifiers.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Timer 1 has two interrupts on STM32F0: TIM1_BRK_UP_TRG_COM_IRQn (13) and
TIM1_CC_IRQn (14). "brk" interrupt name does not reflect all the events
supported by the interrupt, so it has been renamed to "brk_up_trg_com".
On all other series except G0 timer 1 has a specific interrupt for each
event, so in such case "brk" is just fine.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU. It uses
a multiplex before any NVIC interrupt line. The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.
Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
The psoc6.dtsi file declare a reference to nvic. Since it was proper
defined at psoc6_cm0/4.dtsi files this entry is redundant. Drop the
useless entry.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add an emulation controller which routes eSPI traffic to attached
emulators depending on the selected chip(mostly host).
This allows drivers for eSPI peripherals to be tested on systems
that don't have that peripheral attached, with the emulator handling
the eSPI traffic.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Enable slave support for I2C device instances. Slave mode is
interrupt based, wheras master mode is still based on polling.
Remove ENI bit in master configuration since it is not needed for
master mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Add the girq and girq-bit fields to the binding. This allows
encoding GIRQ related information inside device tree.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Initial driver and sample application of
TDK Invensense ICM42605 6-axis motion sensor.
This driver provide DTS for nRF52 DK board DTS setting.
Providing features are below.
Sensor data streaming - Accel, gyro
Tap, Double tap triggering.
Set/Get FSR, ODR by set attr API
Support multi instance feature.
Signed-off-by: JuHyun Kim <jkim@invensense.com>
Add radio peripheral to nrf52833 DTS including antenna matrix
congiuration for Direction Finding extennsion.
Add appropriate binding file for nRF radio peripheral.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The ksz8794 yaml file provides information regarding device tree's
properties for this particular DSA switch IC.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Move all PCIe-based DT nodes under a PCIe bus and take advantage of
the DT_ANY_INST_ON_BUS_STATUS_OKAY() and DT_INST_ON_BUS() macros.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The only two supported operations for data caches in the cache framework
are currently arch_dcache_flush() and arch_dcache_invd().
This is quite restrictive because for some architectures we also want to
control i-cache and in general we want a finer control over what can be
flushed, invalidated or cleaned. To address these needs this patch
expands the set of operations that can be performed on data and
instruction caches, adding hooks for the operations on the whole cache,
a specific level or a specific address range.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Kconfig allowed selecting any bit in the status register as the QE
bit, and defaulted it to 6. Devices need not require a QE bit at all,
and where JESD216 defines QE bit location the only place in first SR
byte that it can be is bit 6. Further, the code unconditionally wrote
the value 0x40 without respecting configuration of other bits. Some
of those bits control write protection of block-protected areas and
should not be changed.
Remove the Kconfig, instead using the jedec,jesd216-controlled
devicetree property. Allow the driver to recognize whether or not
setting the bit is required, and when it is only use bit 6. Only
update if the setting does not match the configuration.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW15 provides information on entry and exit from QSPI modes. In
particular, it specifies whether and how the status register must be
updated for this feature.
Add a JESD216 devicetree property for the Quad Enable Requirements
value.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add definitions for UART1/2 when they're accessible through fixed MMIO
addresses (instead of PCIe), and mark all UARTs not normally available
with the UEFI BIOS as "disabled".
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add a binding to represent a PCIe bus. This way PCIe devices can be
ordered under a parent PCIe bus object and make help of DT BUS macros
for conditional code.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move iis2dlpc trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The BBC micro:bit v2 is a mini-computer that has been
designed to make the coding fun and easy to learn.
The micro:bit v2 is completely programmable so you can
easily bring your ideas to life! From making games to
creating music and even controlling robots.
The micro:bit comes with neat hardware such as a 25 LED
display, buttons, in-built speakers, Bluetooth 5 & Mesh
connectivity and sensors for temperature, motion & light.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
This property is required information for extracting PSEL bits relevant
to peripheral pinmux from this node.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add some details to help new users learn how to manage the nodes
for compatibles corresponding to IP blocks on Nordic SoCs.
The focus is on IP blocks where the pinmux is configured in
devicetree. These typically have individual properties for each pin,
like a SCK pin on a SPI peripheral, which correspond directly to a
PSEL register value. These violate the usual devicetree convention of
using a 'foo-gpios <&gpioX ...>' phandle property and work in ways
that only make sense if you understand the underlying register map, so
it's worth explaining them a bit more carefully.
Skip these two bindings, which have no drivers: nordic,nrf-i2s.yaml,
nordic,nrf-pdm.yaml.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
'reg' attribute removed from overall stm32l1 dts,
so eeprom size has to be specified for each SoC
in stm32l1x series.
Adds remaining stm32l1x SoCs that didn't have eeprom size specified yet.
Eeprom size added in stm32l151Xb-a & stm32l151X8-a dtsi files,
(based on device overview in datasheet DocID024330 Rev 5).
Eeprom size added in stm32l151Xb dtsi file (based on
device overview in datasheet DocID17659 Rev 12).
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add device tree description for qspi node on STM32L4 and
signals on whole family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Setting clock-frequency as required (the driver does not build without
it) and dropping definitions that are already specified in
i2c-controller.yaml.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Replace few instances of space before colon in the binding files, not
functional, just for coherency.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
after 7c699348a8
Convert drivers to new DT device macros
now the device name is aligned with label so we need
align them to default config
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Peter Bigot