This board got forgotten when we migrated the older APIC_TIMER users.
Now the platform is SMP by default and the older driver refuses to
build.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Work around the fact that llvm objcopy does not support --gap-fill right
now. This should be done on the toolchain level at some point, it is
currently not possible however.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
These are all PC systems which have large amounts of memory
which needs to be mapped at runtime (most are 2GB).
Increase the address space size accordingly, adding an extra
8MB for mappings.
The ACRN target has 8MB, give it 16MB of VM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.
We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.
The default address space size is now 8MB, but this can be
tuned by the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.
We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.
The default address space size is now 8MB, but this can be
tuned by the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For a while now, we've had two APIC drivers. The older was preserved
initially as the new (much smaller, "new style") code didn't have
support for Quark interrupt handling. But that's long dead now. Just
remove it.
Note that this migrates the one board using this driver (acrn) to
CONFIG_APIC_TIMER instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These are set such that we have enough pages in the pool
for typical driver mappings and to instantiate two more
memory domains, which is what our tests require.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
- added CONFIG_X86_64 since ACRN hypervisor supports x86_64 capable
platforms only.
- removed CONFIG_SET_GDT: Zephyr doesn't support it in x86_64, and ACRN
doesn't require the guests to setup GDT during boot time.
- added CONFIG_X2APIC, which is preferred by ACRN, which makes it
possible to pass through local APIC to the guests.
Signed-off-by: Zide Chen <zide.chen@intel.com>
XIP support in x86 was something of a mess. This
patch does the following:
- Generic ia32 SOC no longer defines a "flash" region
as generic X86 devices don't have a microcontroller-
like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
The board definition must provide a flash region definition
that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
removed.
- qemu_x86 has a fake flash region added, immediately after system
RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
XIP by default, plus an additional test to exercise XIP on
qemu_x86 (which supports it but has XIP switched off by default)
The overall effect of this patch is to:
- Remove XIP configuration for SOC/boards where it does not make
any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
it off by default for other tests, to ensure it doesn't bit-rot
and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.
Fixes: #18956
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Based on prior work by @dcpleung. It's suboptimal, but it provides a
working starting point for ACRN work. The x86 board/SoC abstractions
really need to be refactored to make this "board" (and other x86-based
"boards", both extant and future) cleaner and easier to maintain. Punt.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Andy Ross