Enable the SPI driver on the HiFive 1
This makes the following configurations choices for the HiFive 1:
The SPI 0 peripheral driver is not enabled by default because it is in
charge of mapping the SPI flash into memory. This can be configured
using the CONFIG_SIFIVE_SPI_0_ROM KConfig option.
The SPI 1 peripheral driver is enabled by default and the pinmux is
configured for all of its outputs
The SPI 2 peripheral driver is enabled by default because it is present
in the DTS for the FE310, but because the QFN48 package used on the
HiFive 1 doesn't route those pins from the silicon die, the pinmux can't
enable the SPI 2 pins.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
FE310 is the name of one SoC out of a range of products in the SiFive
Freedom line. The FE310 SoC port in Zephyr is compatible with all of
these products, so rename the SoC to SiFive Freedom
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit moves code from fe310 platform into RISC-V privilege common
folder. This way the code can be reused by other platforms in future.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
Added support for the HiFive1 board from SiFive
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
Nathaniel Graff