Commit Graph

14 Commits

Author SHA1 Message Date
Sebastian Bøe 347f9a0a2d cmake: LD: Specify the entry point in the linker scripts
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.

This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command

ENTRY(CONFIG_KERNEL_ENTRY)

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-07-03 17:18:14 -04:00
Ulf Magnusson 3ac3216d89 soc: defconfig: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Sebastian Bøe 0829ddfe9a kbuild: Removed KBuild
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
Andrew Boie e434260e19 xtensa: soc: fix IRQ table
The linker scripts were not properly updated to the new
gen_isr_tables mechanism.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-16 10:59:10 -07:00
Leandro Pereira 99181eb661 arch: xtensa: Move exception table to xtensa_intr.c
This cleans up the exception handling by removing the table declaration
from xtensa_intr_asm.S, and removing the unused
_xt_set_exception_handler() function.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira 27ea2d8eb7 arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr.  Some things are still
unconverted, mainly the exception table, and this will be performed
another time.

Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Anas Nashif 397d29db42 linker: move all linker headers to include/linker
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-18 09:24:04 -05:00
Max Filippov 59926490be xtensa: move #include <linker/common-*.ld> up
Move linker/common-rom.ld between .rodata sections so that it's together
with other immutable data.
Move linker/common-ram.ld before the .bss section, so that .bss does not
appear between data sections, which had two consequences:
- there's a .bss-sized gap in the ELF image, and
- PHDR segment that covers .bss overlaps the segment that covers .data,
  resulting in the following xt-run warning:

  ( [ sample_controller ] load_bfd ) *WARNING* Executable segment
    [ 60004d60, 600079a7 ] overlaps an existing executable segment

Change-Id: I2db46f4656e240016fe60883057cc000b6377180
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-20 16:01:18 +00:00
Andrew Boie 11ee791b32 xtensa: build similar to other Zephyr arches
* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:06 +00:00
Mazen NEIFER cb745e6047 Xtensa port: Fixed RAMABLE_REGION in linker scripts.
This was introduced during a copy/paste when updating patch
https://gerrit.zephyrproject.org/r/#/c/10323/6..7

Change-Id: Id6857dd28a16974361932285b44559f702c4d910
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER af2593ea7e Xtensa port: Added linker script for several Xtensa cores.
Change-Id: I7a40d5f0c3fe8d25623b88f06523cb62e4ba4706
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER e2dd006ba7 Xtensa port: Removed the need to put an empy file soc.c in arch/xtensa/soc dir.
Change-Id: I439a6c36f10c6255d15a688c8f425de0fab93912
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 1cded67f38 Xtensa port: Started port to for Xtensa cores family.
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.

Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:26 -08:00