Commit Graph

8 Commits

Author SHA1 Message Date
Tomasz Bursztyka 17c6456678 drivers/uart: Use dts to set uart priorities for QMSI driver
Fix the qmsi uart driver and relevant SoCs accordingly.
Also: using config for irq everwhere relevantly and not an hardcoded
value in the driver.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Kumar Gala 461b5018d3 serial: introduce SERIAL_SUPPORT_INTERRUPT Kconfig option
As not all drivers support interrupts we don't have a means to know if
we can allow UART_INTERRUPT_DRIVEN to be enabled and thus various
Kconfig options that select UART_INTERRUPT_DRIVEN.  Some drivers have a
interrupts, however not all do.  So introduce a Kconfig option to let us
know what the driver actually supports.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-06-29 07:07:31 -04:00
Savinay Dharmappa 0ea423d976 drivers: serial: Add device support for serial driver
patch enables qmsi serial driver to pick baudrate and name
from device tree instead of Kconfig for UART0 and UART1
instance

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-06-22 10:23:39 -05:00
Johan Hedberg 6f6984129a drivers: uart_qmsi: Re-enable HW FC for arduino_101 & quark_se_devboard
On current Curie-based boards UART 0 is wired to the nRF51 BLE
controller and requires HW flow control to be enabled in order to
function. This patch restores the same behavior that was present
before the "qmsi: uart: use built-in qmsi driver" patch.

Change-Id: If7ea347f5ab8b460f39123dcc0d75d711a5a1c2a
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-04-25 11:42:50 +00:00
Anas Nashif 1797c8f108 qmsi: uart: use built-in qmsi driver
Change-Id: Ie19aee8dad8ba082891f92a2d42dc71f4ac34dbe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Andre Guedes 7633279d4a uart: qmsi: Add support for IRQ APIs
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.

Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.

Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.

Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 23:55:13 +00:00
Andre Guedes 27b548251e uart: qmsi: Add baud rate configuration support
This patch extends the UART QMSI driver so it supports different baud
rate configurations. The baud rate is set per UART controller via
menuconfig. The default baud rate is 115200.

Change-Id: Iad736d72bd309b8a33ab5d538251fce374e89fd2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 23:55:04 +00:00
Andre Guedes d95d6c63a1 uart: Introduce QMSI shim driver
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.

This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.

In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y

This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.

Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 23:54:59 +00:00