Adds a board-level config option to select whether the code gets linked
into internal instruction tightly coupled memory (ITCM), external
hyperflash, or external qspi flash. The default is ITCM.
Note that we are not yet building an image vector table (IVT) into the
image, therefore the zephyr binary is not bootable by the SoC ROM as-is.
However, the DAPLink firmware prepends an IVT to the image when you use
its drag-and-drop feature to program flash, and this results in a
bootable zephyr application.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds
hyperflash, qspi, and sdram external memories to the mimxrt1050_evk
board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Underscore ('_') isn't a valid char for alias names based on the device
tree spec. Newer dtc compilers flag this as a warning so lets clean it
up. Replaced '_' with '-' to keep things simple.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Maureen Helm