They were the same, standardize on the lowercase one.
Change-Id: I8bca080e45f3e0970697d4451e468b9081f96f5f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Gets rid of unnecessary THREAD_MONITOR_INIT() macro, to be
consistent with the approach taken by _thread_monitor_exit().
Aligns x86 code with the approach used on other architectures.
Revises the associated comments and removes unnecessary
doxygen tags.
Change-Id: Ied1aebcd476afb82f61862b77264efb8a7dc66c9
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
- the interrupt (both regular and fast) now does not do rescheduling
if the current thread is a coop thread or if the scheduler is not locked
- the _nanokernel.flags cache of _current.flags is not used anymore
(could be a source of bugs) and is not needed in the scheduling algo
- there is no 'task' field in the _nanokernel anymore: scheduling routines
call _get_next_ready_thread instead
- the _nanokernel.fiber field is replaced by a more sophisticated
ready_q, based on the microkernel's priority-bitmap-based one
- thread initialization initializes new fields in the tcs, and does not
initialize obsolete ones
- nano_private includes nano_internal.h from the unified directory
- The FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
priority drives the behaviour
- the tcs uses a dlist for queuing in both ready and wait queues instead
of a custom singly-linked list
- other new fields in the tcs include a schedule-lock count, a
back-pointer to init data (when the task is static) and a pointer to
swap data, needed when a thread pending on _Swap() must be passed more
then just one value (e.g. k_stack_pop() needs an error code and data)
- the 'fiber' and 'task' fields of _nanokernel are replaced with an O(1)
ready queue (taken from the microkernel)
- fiberRtnValueSet() is aliased to _set_thread_return_value since it
also operates on preempt threads now
- _set_thread_return_value_with_data() sets the swap_data field in
addition to a return value from _Swap()
- convenience aliases are created for shorter names:
- _current is defined as _nanokernel.current
- _ready_q is defined as _nanokernel.ready_q
- _Swap() sets the threads's return code to -EAGAIN before swapping out
to prevent timeouts to have to set it (solves hard issues in some
kernel objects).
Change-Id: Ib9690173cbc36c36a9ec67e65590b40d758673de
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
EM7D was recently merged, and one change suggested there was
to remove conditional checks for NSIM. It is OK to have the simulator
use the exact same memory addresses and sizes as would be found on the
board. This submission fixes EM9D and EM11D to be the same -- i.e.
to not have NSIM conditionals.
See ZEP-966.
Change-Id: Ia990ff7bb4b7ff5071af83723ed3d1420fdff012
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The EM7D SOC is similar to EM11D, except it has different sized
iccm and dccm memories, and also has FIRQ with RGF_NUM_BANK==1.
To select this SOC on the board, all dip switches are in the up position.
See ZEP-966.
Change-Id: I864ffe0efdf367de0a8cd58e9c46efd7e401c671
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The code density registers are NOT saved on the stack.
This is controlled by bit 13 in AUX_IRQ_CTRL, which didn't even have a symbol
defined for it. I've also added _ARC_V2_AUX_IRQ_CTRL_LP for bit 13.
Change-Id: Ie80853b72bed4e60a5cf1cf0a8c905a3d86180d9
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
In order to add the EM7D SOC, I will be implementing a version of the FIRQ
interrupt handler that saves and restores registers on the stack when
RGF_NUM_BANKS==1. All other ARC SOCs at this time have RGF_NUM_BANKS==2,
allowing for a faster handler that can use the registers in the 2nd register bank.
But EM7D doesn't have this 2nd bank, hence the need for this new configurable choice.
(See ZEP-966)
Change-Id: Ie089f1f079902552cf279c2cda23ee0805b01eed
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
i2c_quark_se_ss driver is deprecated and replaced
by i2c_qmsi_ss. So remove i2c_quark_se_ss definition.
Change-Id: Idcc6a7f01ffae626ae7d5f9966eac67be78599af
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
commit e57b21c78c ("irq: Use lowest priority not a
hard-coded priority 2") introduce a wrong whitespace,
not complying with coding style. Remove it.
Change-Id: Ie7e48843e5da6cb3417773ef8a57cf9a166c70d6
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
In this file was found an assumption about how many
priorities are being used. This is configurable with
CONFIG_NUM_IRQ_PRIO_LEVELS, however, so it should be using that
instead. This line of code changes:
or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1))
so as to use the correct bit to OR.
Change-Id: I8c6297e98b5163aa27460a68b203e8a27d1e2506
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Set _ARC_V2_DEF_IRQ_LEVEL to the last legal priority value, and not 15.
The last legal value is: (CONFIG_NUM_IRQ_PRIO_LEVELS-1).
This is safer because we don't want priorites not configured to be
enabled.
Change-Id: I1689cc00aa7e707a204d16ec17d7f396566e8638
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
No need to create new Kconfig that do exactly the same, just
reuse those from the main QMSI driver.
Change-Id: I965055f36845ac0464e4a383b0d05c3ae35c0015
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The ARC side should use the same console UART as x86 by default if we
want identical behavior.
Change-Id: I067860581cfd93d97ffad3d8f0bc5591f555e3ce
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Change the signal ramp up/down config parameters in i2c driver
module to SoC specific.
Jira: ZEP-753
Change-Id: Ie01f1d890a7133d30ea53eee07f60354734a8571
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Treat the sensor subsystem as an independent board that can send
messages to UART and disable IPM and the messaging interface. IPM
can be enabled by applications that require such interface.
Fix all samples that are affected by this change to make sanitycheck
pass.
Jira: ZEP-451
Change-Id: I3df6af16adefaefec02b97778d6c68ffc920ac35
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
These files were almost exactly the same and had already started
bit-rotting (note the missing net_l2 section in linker_harvard.ld)
Issue: ZEP-528
Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Defined in all SoCs, but never referenced anywhere. That definition has
been replaced by CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Change-Id: I1801f72a03925717ded6fbfdef22b1993f843461
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
0 should be fine; no need to make this an FIRQ or non-maskable
Change-Id: Ifdf89a72e4864a2c2bbd83752cd814e2cb9aa16e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The GPIO and UART drivers were failing to build due to some
missing soc.h defines.
Change-Id: I6811e3699449da0a61ccc8376a8e11b96ad7a4e5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
CONFIG_SOC_GENERIC_ARC doesn't exist so remove it.
Change-Id: Idecfd27684b5fd83b7b296daa46a1a21a0ae4d95
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The comments for INT_ACTIVE and EXC_ACTIVE now refer to
"executing context ..." for all architectures.
Change-Id: Ib868958639a3b30e1814fcaa4d1f0651d3b2561e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There are a few problems with the code being repaired here.
1. A seti was used to re-enable all interrupts, even though the
thread being switched to may have had certain interrupt priorities masked.
2. saved status32 already has SC bit if thats wanted, so its ok to just
restore status32 as-is w/o needing to and off anything.
3. the code is difficult to write using kflag and seti because as you
restore registers, there aren't any to use. But we can exploit a
trick where we pretend an interrupt has occured by setting a bit in
AUX_IRQ_ACT, and then use RTIE instruction to restore status32
atomically with branching to return address. Something about the way
this code was written was causing stack corruptings and crashes in an
application that uses a high rate of both FIRQ and Regular interrupts.
Change-Id: Ia7166d51f0e750c07832ab115b7151ce37ee0278
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Since firq utilizes a 2nd register bank, and since all of those
many GPRs can be used, the strategy here is to save extra registers,
such as lp_count, lp_start, lp_end into callee saved registers.
These registers are safe to use because the C-ABI followed by the
compiler will cause these to be spilled to the stack if a C function
wants to use them. By selecting upper GPRs, r23-r25, it is very unlikely
the compiler will spill them. This improvement, therefore, can avoid a
d-cache miss since we are avoding memory altogether when saving these.
The struct firq_regs is no longer needed.
Change-Id: I7c0d061908a90376da7a0101b62e804647a20443
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
It was found that the test latency_measure, when compiled
for microkernel, would fail on the ARC. This because the
trap handler, used by irq_offload, wasn't supporting thread switching.
This submission adds the code to do that, and the code size is
bigger only when CONFIG_MICROKERNEL is defined.
To keep code a bit smaller, there is a trick exploited here where
the AE bit is cleared in the STATUS32 register and in AUX_IRQ_ACT,
bit 1 is set, to make it appear as if the machine has interrupted
at priority 1 level. It then can jump into some common interrupt
exit code for regular interrupts and perform an RTIE instruction
to switch into the new thread.
test/latency_measure/microkernel now passes.
Change-Id: I1872a80bb09a259814540567f51721203201679a
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Introduce a soc-cflags, soc-cxxflags, and soc-aflags as a means for
SoC specific compiler flags to be set without manipulating Kbuild
options directly.
Change-Id: I2c8f5019fb237429e59717ef96bd4251a61dc1a5
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The .nd on a branch is WRONG if its an unconditional branch. Not needed.
On conditional branches its a compiler feature that is not yet functional
with ARC targets. Typical code for this compiler can use .d to put
something in the delay slot of an instruction, but using .nd is probably
never wanted.
Change-Id: If1017c468e6e7af269ea73daeb4bc223dcc0059f
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Microkernel on ARC works fine, was missing some declarations in the
linker file.
Also enable testing of microkernel with ARC and disable tests where
ARC is not supported yet.
Jira: ZEP-396
Change-Id: I2ac7b8dc0bea22f5d2e24832d9e3afad8df9f580
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add missing Kconfig files and connections to expose Kconfig options
in ext/ directories. Fixup QMSI to only be exposed on platforms that
utilize it.
Change-Id: I6c6c5011b2bf2966f65aa8279dc594a244821956
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The ARC CPU comes up from reset with i-cache enabled.
It can have garbage in it from a previous run.
The fix is to check the build register for the i-cache, and if its
present, invalidate it fully, and then disable it.
_icache_setup() is called later to turn it on.
Change-Id: I26fae915153841c61e9530d5af2ddb9d0553275b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
EM11D is a ARC CPU configuration that can be selected for the
ARC EM Starter Kit. The board support for this board will be
submitted separately to expidite review.
Change-Id: Ifc4d48e1f5e01d44d1706e6426bd3b2d77ebe2f8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
EM9D is a ARC CPU configuration that can be selected for the
ARC EM Starter Kit. The board support for this board will be
submitted separately to expidite review.
Change-Id: I2c85bdab6ea7bfb257e94e4c72b11b4568dbac19
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Benjamin Walsh