The PLLR parameter in LL_RCC_PLLI2S_ConfigDomain_I2S() API should
be selected among the following list of (already shifted) values:
* @arg @ref LL_RCC_PLLI2SR_DIV_2
* @arg @ref LL_RCC_PLLI2SR_DIV_3
* @arg @ref LL_RCC_PLLI2SR_DIV_4
* @arg @ref LL_RCC_PLLI2SR_DIV_5
* @arg @ref LL_RCC_PLLI2SR_DIV_6
* @arg @ref LL_RCC_PLLI2SR_DIV_7
This commit fixes PR #12609.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Check clock_control_on return value now that it is checking appropriate
bus is used in the request.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align the dma_callback() signature to the new one in order
to avoid warnings during compilation.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
STM32 I2S driver implementation. It has been designed in the most
generic way possible, with the possibility of using it in master/slave
and rx/tx mode. Currenty it has been tested for master rx mode only
using the microphone on ArgonKey board.
The configuration file permits to compile it for STM32F4xx product
family only, but it should be easy to extend it also for other
families.
It supports all 5 STM32F4xx I2S controllers (I2S 1/4/5 on APB2 and
I2S 2/3 on APB1).
It makes uses of the available DMA channels for rx/tx streams.
The clock source can be selected among one of the following two choices:
- PLLI2S pll, with possibility to configure PLLM/PLLN/PLLR
- HSE/HSI clock
Interrupt is triggered only in case of errors (FRM/OVR/UDR).
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Armando Visconti