Use sizeof instead of strlen to get the correct buffer
length and initialize rx buffer with zeros before the dma
transfer.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This will prepare test cases and samples with metadata and information
that will be consumed by the sanitycheck script which will be changed to
parse YAML files instead of ini.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change reference voltage for Analog comparator to Internal reference
voltage.
Currently AIO is using External reference voltage (Reference A) and
external reference is set at 3.3V. In this usecase both reference
Voltage and AIO IP are set at 3.3V. So rising edge interrupt behaviour
will be unpredictable.
So by changing internal reference voltage to Internal (set at 1.09V)
interrupt will be generated as soon as Voltage on I/P will exceed it.
Jira: ZEP-1927
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
AIO should be supported on more platforms. Adapt
this case to make it run on more platforms.
Also keep reference voltage for comprator as internal.
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
There're (at least) 2 UART TX interrupt causes: "tx fifo has more
room" and "transmission of tx fifo complete". Zephyr API has only
one function to enable TX interrupts, uart_irq_tx_enable(), so it's
fair to assume it enables interrupt for both conditions. But then
immediately after enabling TX IRQ, it will be fired with "tx fifo
has more room" cause. If ISR doesn't do anything to fill FIFO, on
some architectures, immediately after return from ISR, it will be
fired again (with no instruction progress in the main application
thread). That's exactly the situation with this test, and on ARM,
it leads to inifnite IRQ loop.
So, instead move call to uart_fifo_fill() inside ISR, and be sure
to disable TX IRQ after we transmitted enough characters.
Change-Id: Ibbd05acf96b01fdb128f08054819fd104d6dfae8
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
We reserve a specific vector in the IDT to trigger when we want to
enter a fatal exception state from software.
Disabled for drivers/build_all tests as we were up to the ROM limit
on Quark D2000.
Issue: ZEP-843
Change-Id: I4de7f025fba0691d07bcc3b3f0925973834496a0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I6c676bc6c5e850a8725785554cd535e32067f33e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ztest has a number of assert style macros and used a baseline assert()
that varies from the system definition of assert() so lets rename
everything as zassert to be clear.
Change-Id: I7f176b3bae94d1045054d665be8b5bda947e5bb0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverity points out that uart_irq_update() return value
should be checked.
Coverity-CID: 166776
Change-Id: I3a754dae9e8f1563f4879e2fadfd89621785de8f
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
The test failed to initilise these to known states, so fix this by
asking for end of transfer and error callbacks.
Change-Id: I523168381329062ec0c17aa41cb4033b78d8ed99
Signed-off-by: Jon Medhurst <tixy@linaro.org>
These were flagged by icx build.
Jira: ZEP-1887
Change-Id: Iaeedb13be23e86ebfb29a6441574b7384ae836e1
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
Add pin definitions to enable GPIO cases to run on
Quark D2000.
Add pin definitions to enable GPIO cases to run on
arduino_101_sss.
Change-Id: I97eadb8316b1f80b899b167a01effab815626dae
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
According to ZEP-1717, removing the callback from
the gpio is not enough to disable interruptions.
You also need to call gpio_pin_configure() on
the input pin without the GPIO_INT flag to totally
disable the interrupt for the pin.
This commit will stop level interrupt from being
fired constantly.
Change-Id: I019d7cea0bc0d5e5ff4b74165472ed11de1733bb
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
These were flagged by icx build.
Jira: ZEP-1864
Change-Id: I5b8fce64d9e20d768fabf02e2a799e9390e3679a
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Depending on test environment, termination character could
be '/r' instead of '/n'.
Enabling both possibilities.
Change-Id: I18b47e9055667e0a4f868416ee8d01226a879712
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order for interrupt reset mode to work (reset the processor
after and interrupt) the interrupt does not has to be cleared,
and the qmsi hal layer clears the interrupt after the callback
has been invoked, the callback does not return and the processor
should reset.
Jira: ZEP-1566
Change-Id: Ic951a0f15fe95fb0ef5d752b831c62e6fa3ceea0
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
The include guard has a misspelling.
Jira: ZEP-1746
Change-Id: I4d8000ef5c8e037f80acbf2491d0b9466670816a
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
Some files made it through review process with full license header.
Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This was reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: Ib97ed8da830126c9fbfa2269c8b2327d2f1be2f4
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
When test GPIO_INT_EDGE, there is no code to skip GPIO_INT_LEVEL
and jump to the end of the function. So GPIO_INT_LEVEL will
always be checked (Besides, it't always true), even if it's
testing GPIO_INT_EDGE, which will cause GPIO_INT_EDGE cases fail.
Add a goto statement for GPIO_INT_EDGE to skip GPIO_INT_LEVEL.
Jira: ZEP-1685
Change-Id: I10ce21c04c49f34aafdc2cd2f60f3e5377d6f1f5
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
This test case uses PWM0 port to test PWM on Quark Se.
However PWM0 port on Quark D2000 is initialized as tdo,
not PWM0 and disabling tdo will kill JTAG on D2000. So
use PWM1 and add PINMUX setting code to configure PIN_24
as PWM1 port, then the case will work on D2000 board.
Change-Id: Ib28d4750dac7396529388b781fb64bde048139d6
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
the commit test below adc driver api with different resolutions
and modes
adc_enable()
adc_read()
adc_disable()
move original adc test to adc_simple folder
Change-Id: I016b5e67a5d89fc8d5ae76f33799e5d3eb3e1cf8
Signed-off-by: jing wang <jing.j.wang@intel.com>
Update the dma loop transfer sample app to use the new
dma api interfaces. This change is based on the api change
and the updated dma driver.
A RFC was posted recently on this.
Jira: ZEP-873
Change-Id: I289e2e08d4c775a833bf3d585d2706a903edd0bc
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Update the dma block transfer sample app to use the new
dma api interfaces. This change is based on the api change
and the updated dma driver.
A RFC was posted recently on this.
Jira: ZEP-873
Change-Id: Icf3bec7260c2e499485b07a4a579956448a1a3fd
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Remove dev driver and integrate it in the default pinmux driver.
Jira: ZEP-958
Change-Id: I55670240f8a21749d3a6ae22e300e16ba80a2fb6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to include/gpio.h, GPIO_INT_LEVEL is 0,
which means the branch to test GPIO_INT_LEVEL is
always false and GPIO_INT_LEVEL cases will always
pass.
This patch also fixes another minor bug in main.c.
Coverity-CID: 160074
Change-Id: I1fefa978e65bf801f244b4c2960cb87a26b0829e
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
According to Coverity, rand() is a risk function.
So we use another method to generate random value.
Coverity-CID: 160070
Change-Id: Icb7e06cd43cb8bade6596cc37e9d04bfc59e1de7
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The commit verify below PWM apis
pwm_pin_set_cycles()
pwm_pin_set_usec
test PWM apis under always-on, half-on and alway-off modes
Change-Id: I2251be23ad9c443703dac44e138651a63d2d7211
Signed-off-by: jing wang <jing.j.wang@intel.com>
Merges the ksdk pinmux dev driver into the regular ksdk pinmux driver,
which now exposes the public pinmux API. Removes the private ksdk pinmux
API and converts the frdm_k64f and hexiwear_k64 boards to use the public
pinmux API.
Jira: ZEP-958, ZEP-1432
Change-Id: Ie5f60b604133093050b9c596050cad776d7b7cb3
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
A few CONFIG options got set twice in sensors_n_z.conf, remove the
duplicates as we get warnings associated with this:
warning: override: reassigning to symbol GPIO
warning: override: reassigning to symbol SENSOR
warning: override: reassigning to symbol SPI
warning: override: reassigning to symbol SYS_LOG_SENSOR_LEVEL
Change-Id: I7a723218db8e365bdb45c004e93bd2c4f55ab5ac
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove legacy option and use SYS_CLOCK_EXISTS where appropriate.
Change-Id: I3d524ea2776e638683f0196c0cc342359d5d810f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To customise test builds and support test related features such as time
stamps and a boot banner, introduce a Makefile variant that is dedicated
to testing.
Initially we introduce a new config overlay that is used for all tests, in
this case we enable BOOT_BANNER and BUILD_TIMESTAMP. This will print the
current version and the date, useful when reporting bugs and also an
indicator that the system has booted before the test has started.
For example:
[QEMU] CPU: qemu32
***** BOOTING ZEPHYR OS v1.6.99 - BUILD: Dec 21 2016 19:57:13 *****
tc_start() - Test Nanokernel CPU and thread routines
Initializing nanokernel objects
...
..
Change-Id: I224318cdeb55a301964ea366dbc577e2e3a09175
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Johann Fischer