Commit Graph

34 Commits

Author SHA1 Message Date
Kumar Gala 9ec2f3be80 Cleanup whitespace in Kconfig files
Convert leading whitespace into tabs in Kconfig files.  Also replaced
double spaces between config and <prompt>.

Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 13:28:07 -05:00
Chuck Jordan a364a628b0 arc: Add CONFIG_HARVARD since some ARC CPU Architectures are Harvard.
Some ARC SOC implementations will need CONFIG_HARVARD so as to
select a different initial stack pointer (one at the top of DCCM memory),
and also to select a different linker command file that uses
ICCM and DCCM. Quark_se_ss will have HARVARD equal to n.

Change-Id: Idb7c4126866c9604e1924200ad5fdd2bc9d28269
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-09 20:56:51 +00:00
Chuck Jordan 77286b3143 arc: Set __start entry point to be same as __reset
There is a BUG here in that the alias for __start was
aliased to the start of the vector table. Yet, on ARC CPUs,
the vector table CANNOT be the entry point, because there
is no code in a vector table. Only addresses appear in each vector.
Thus, the reset vector, at offset 0 in this table, is a raw address.
The top Makefile in zephyr sets the lable __start to be the entry point
like this: -e __start. Debuggers, for example, use this entry point
to know where the first line of code is.

Also, in KConfig, there were duplicate NSIM blocks. One has been
removed.

Change-Id: I480be7d338a8b45b8ea6ef3f55ac2e6c43829452
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-05 22:12:56 +00:00
Chuck Jordan 822b19ef74 arch/arc: add ICCM_BASE_ADDRESS and ICCM_SIZE
I am working on porting Zephyr to ARC EM Starterkit. This board has ARC 
CPUs with ICCM memories. On quark_se_ss ICCM is missing and ignored.

Change-Id: Ic49fc8ef3e6ad879ffc673b8baf34dd467f76c04
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-04 14:54:54 +00:00
Andrew Boie 7327c9ee1f nanokernel: move C atomic operations to centralized code
These C variants of atomic operations can work on any arch,
have platforms select them if they don't have ASM equivalents.

Change-Id: I38eb03bb58beff865681ee56ef7bc0fcded1e906
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-27 21:40:19 +00:00
Anas Nashif 1a1f7fd916 arc: make SRAM/DCCM values configurable
Remove hardcoding and make the values configurable. Also make the
Kconfig variables consistent with other architectures.

Change-Id: I69334002303d4d8abaf7363d9134fd5f46ce4eeb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-25 19:17:03 +00:00
Alexandre d'Alton f91e55b798 arc: implement stack checking
ARC CPU has stack checking feature that allows to trigger an exception
whenever the stack is incorrectly accessed.
This patch implements the stack_top and stack_base register updates on
context switches, and activates the Stack Checking bit of STATUS32
register when the CPU is in the context of a fiber or task.
As GCC accesses the non-yet allocated stack with frame pointer enabled,
this patch also add the omit-frame-pointer gcc flag in order to work
properly.

Change-Id: Ia9e224085a03bd29d682fb8f51f8e712f2ccb556
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
2016-03-29 01:25:49 +00:00
Ramesh Thomas bb19e6f82f power_mgmt: Make names consistent with new RFC
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.

Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-26 14:35:11 -04:00
Daniel Leung ef83c14c4a arch: move kconfig SoC selection to top level
The SoC selections for each architecture are moved to the top level
in menuconfig and xconfig. This makes it more intuitive to select
architecture -> SoC -> then board, avoiding an additional trip to
go into the architecture menu to select SoC.

Change-Id: I57a78a09adfc4bb12423915b6ad14ceb74381a2b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-15 21:39:14 -04:00
Andrew Boie 4a4e82b0c5 arc: remove CONFIG_SW_ISR_TABLE_BSP
It is semantically identical to CONFIG_SW_ISR_TABLE.

Change-Id: Iff0c47166ee6fb1fd8a0991a67bc863d45c32559
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie d9df4758e4 arc: remove SW_ISR_TABLE_STATIC_CUSTOM
This scenario is no longer supported in code; the Kconfig
didn't actually do anything.

Change-Id: Ic48bffb5180c4f72bc9c5d85cf18b1072432b951
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Yannis Damigos baddeadda1 arch: & kernel: Updated Kconfigs to remove errors in html generation
This patch updates some help sections to remove the "ERROR:
Unexpected indentation" messages during hmtl documentation
generation.

Change-Id: Idcdc17727b921b6145f9eb28d85975ceca273ce2
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-03-04 13:26:15 +00:00
Daniel Leung 1d88a8618d arc: remove defaults for IRQ priority levels
The deleted defaults cannot be overriden by defaults defined
in SoC's Kconfig file. The number of IRQ priority level was
always one, and this caused some code to be dropped within
the fast IRQ handling code. When the electrons aligned in
certain way, undesired effects were observed (e.g. exception,
faults, etc.) when regular IRQs were mixed with fast IRQs.

Moreover, ARC cores are high configurable on hardware level.
So let the SoC config define these values instead.

Change-Id: I2a338d2efc814c46b0f68ab100fc0f66ae0fb60c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-26 15:20:10 +00:00
Andrew Boie 2a1ae3f436 ARM: ARC: put sw_isr_table in ROM by default
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.

At some point this config option broke, probably when static
interrupts were introduced into the system.

To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.

Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:21 -05:00
Daniel Leung db2d48b66f arc: add atomic operations for ARC EM family processors
The ARC EM family processors do not support native atomic assembly
instructions (LLOCK and SCOND). Therefore, the assembly version
of atomic functions cannot be used. This adds pure C version of
these atomic functions.

Change-Id: Ic64dd31b0367b6dcf3a46f41c0c7ac2c2ce5eb8d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:16 -05:00
Benjamin Walsh 7e5dd561ca arc: select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
The ARC is an architecture that supports tickless idle in
nanokernel-only systems, and it thus must signal this to the build
system.

Change-Id: I96b0a4e8f78b2ea67d2f1b3384e94a32d8eb80e8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:13 -05:00
Andrew Boie 41bebcd8e0 arc: correctly size the IRQ vector table
CONFIG_NUM_IRQS expresses the total number of available interrupt
lines in the system, and is used to generate a vector table.
On ARC, the vector table is assembled from two parts, _VectorTable
for the first 16 entries (reserved for CPU exceptions), and
_IrqVectorTable for the remainder. The code that creates _IrqVectorTable
was not taking this into consideration and was 16 entries too big.

Change-Id: I676c8534274de8782178f3773bc53a817b89481f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Anas Nashif 3218f53fe0 arc: remove defaults for NUM_IRQS let SoC set it
Let the SoC decide the number of the IRQs. Fixes a bug where
Quark SE gets the default instead of the declared value in the SoC
Kconfig.

Change-Id: I978c923fbe2a0737ace27ec951bc3a46e8976584
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:13 -05:00
Anas Nashif 10bb38c186 Use SoC instead of platform.
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.

Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Andrew Boie 2ec374a8df irq_offload: ARC implementation
Uses the "trap_s" exception to simulate entry into IRQ context;
offloaded functions run on the FIRQ stack.

Change-Id: I310ce42b45aca5dabd1d27e486645d23fa0b118f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif fe29e34369 arc: remove defaults and fixed typo k->K in linker.cmd file
The defauls set in architecture Kconfig are not being overwritten
by the platform, so remove those and rely on platform provided
data.

Change-Id: Ia71d9d14dddce94c29b9ca957b4ed3ae8838d96c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Anas Nashif 4927ff8d75 arc: use integer RAM_SIZE globally
Using int for the Kconfig variable to resolve warnings from Kconfig.

Change-Id: If2574753fd5761b59f37a8bccea8c5f6699cb363
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:53 -05:00
Anas Nashif 77ba3c3b8b kconfig: define architecture as a kconfig variable
Do not depend on environment variables and use a kconfig variable
for defining the architecture.

In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.

Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif 4ca036074d arc: use kconfig wildcards
Use CONFIG_PLATFORM to only build the selected platform. This
makes the makefile with drop-in platforms, does not need to be
changed for any new platforms.

Change-Id: I8720ba1501b6e1929bfec294f5bb1c7466d65049
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif b0b936b51c arc: add Quark SE Sensor Subsystem nanokernel support
Change-Id: I8178076e9f8bf98c3149f3622aa2236070446c62
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif 28af1ee421 Move RAM and NSIM option to architecture level
Change-Id: Ic47e263bebe4bc2fecb233856ddd1f5de85c11d8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif 2ad03b930d define range for FAULT_DUMP config variable
Only allow valid values to be set for this option.

Change-Id: I11dd7381ddbf6d4d9985255b9b784544074aba63
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:37 -05:00
Javier B Perez Hernandez f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Dirk Brandewie c081a6e987 arc: Remove STACK_CHECKING config
STACK_CHECKING is not implemented

Change-Id: I6d00e4121740a1d164d48a1a284940ee653b6925
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Anas Nashif 8976762df8 arc: rename generic platform to generic_arc
The generic name is too generic and when it appears on its
own, for example nano_generic_defconfig, it is not
visible what the file is about, so call it generic_arc the same
way the Kconfig platform is called.

Change-Id: Icf737f305d84142dad4f52fd26a5c7481f9fc5be
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:58 -05:00
Dirk Brandewie 8570e3cac2 arc: add support for generic
Add support for a "generic" ARC implementation. This is a misnomer
since ARC platforms are synthesized by the SOC vendor and are specifc
to a given vendors implementation/configuration.  This platform
support if for an SOC where we are allowed to let the code to support
the SOC into the wild but not allowed to name it in public.

This change allows to work on support for the SOC in the open and let
the rest of the community see the evolution of of the platform.

Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:15:41 -05:00
Anas Nashif b3b16c6323 kconfig: add NSIM option to arch Kconfig
The option is being referended by the same file
but is not being defined anywhere.

Change-Id: I5e0ec4c29cba773a5256bae52190a117fcc12bf3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:35 -05:00
Anas Nashif be26b52406 Sync arch/<arch>/Kconfig files
Put architecture option and ARCH_DEFCONFIG on the top
and simplify default options for the architectures.

Change-Id: I4cae73f3e9ec24913e201269ec6dc8eddc2fd7c1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:33 -05:00
Anas Nashif cfb9332c30 arc: add missing Kconfig/Makefiles to architecture
Change-Id: I99e96853e5ddc9eb0dd9ca9711921d5b57448db7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00