On x86_64, the arch_timing_* variables are not set which
results in incorrect values being used in the timing_info
benchmarks. So instrument the code for those values.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For x86, TSC is being used to gather timing information. However,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is not the same as TSC
frequency when HPET (or other) timer is used. So use the system
clock to calibrate the TSC frequency so we can use it to
calculate timing information.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The sidebar for User Mode wasn't set up correctly and
it wasn't obvious that there are linked sub-pages with
design details about memory domains, system calls, kernel
objects, and so forth.
Split the introductory material into its own overview
page and set up the table of contents properly.
The text of the threat model, high level policy details,
and constraints sections is unchanged.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ZephyrExtension package allow downstream users to extend the current
Zephyr package.
A ZephyrExtension package allows for setting of additional DTS_ROOT,
BOARD_ROOT, and similar variables without having to patch Zephyr repo.
The repository or folder containing the ZephyrExtension package must be
on toplevel in the Zephyr workspace.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Allow configuring the clock prescaler divider for the NXP Kinetis
FlexTimer. Setting the prescaler to a lower value allows for much
higher resolution/accuracy for the generated PWM waveforms.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Map Arduino interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by Arduino.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Map mikroBUS interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by mikroBUS.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Adds support for a new SHIELD, Eth Click.
Mikro-BUS type shield supported in Zephyr.
Adds Kconfig for mikroe_eth_click shield.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
If build with full POSIX API, use read()/write() instead of
recv()/send() calls for sockets.
We have read()/write() support for a while, but no samples/tests
actually performed at least a build test for it (so it will be
done now).
Fixes: #25407
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
User can now add extra Ethernet TAP parameters when starting QEMU.
This is useful if we want to set for example the MAC address
of the network interface.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Give instructions how to run multiple Zephyr instances in QEMU
or native_posix, and connect them together.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
build breakage if SMP is disabled
In function `bt_unpair':
bluetooth/host/hci_core.c:2640: undefined reference to `bt_foreach_bond'
Signed-off-by: chao an <anchao@xiaomi.com>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DISK_ACCESS_STM32_SDMMC flag to for each SDMMC pinmux
configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2S flag to for each i2s pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_CAN flag to for each can pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DAC flag to for each dac pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_ADC flag to for each adc pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_PWM flag to for each pwm pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2C flag to for each i2c pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SPI flag to for each spi pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit updates the documentation so that it no longer requires
ZEPHYR_SDK_INSTALL_DIR and ZEPHYR_TOOLCHAIN_VARIANT to be used when
using the Zephyr SDK.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
test_testsuite_class.py: Add testcases for add_testcases function
of testsuite class in sanitycheck.
test_data/testcases/tests & /samples : Testcase root directory
to add all the testcases & to test add_testcases function.
conftest.py: Module for common pytest fixtures, also used for
passing data from one testcase to another.
Note: conftest.py has a class_testsuite fixture where board_root is
defined as the directory which will be added in a separate PR.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
The device structure definition in the code has drifted from the
displayed version in the documentation. Update the documentation to
match.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The underlying structure is not suitable for use in API invoked from
user threads for the reasons explained in the edit.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Extend the provided template with annotated examples of API based on
whether the functions must be invokable from user mode threads, since
there are currently no in-tree examples of the specific techniques
required.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Kernel objects were being directly accessed without previously
calling k_thread_access_grant().
This change allows each test that requires an asynchronous
event to send it to a common work queue with correct
permissions.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
There was a possible race condition between sock_is_nonblock()
and k_sem_take() in spair_read() and spair_write() that was
mitigated.
Also clarified some of the conditional branching in those
functions.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
According to below rule which's from DWARF5 sepc, if the
attribute can't be founded in given DIE, check more entry
associated by DW_AT_abstract_origin.
For the purposes of determining whether a debugging information
entry has a particular attribute (such as DW_AT_name), if
debugging information entry A has a DW_AT_specification or
DW_AT_abstract_origin attribute pointing to another debugging
information entry B, any attributes of B are considered to be
part of A.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
On some STM32 boards : nucleo_wb55rg, nucleo_l152re
the test lasts longer than defaut 60sec timeout.
Increase timeout to 120 sec.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.
Fixes#25337
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This makes the up_squared board default to x86_64.
This also adds a new board, up_squared_32, for when 32-bit
is desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
UARTs and I2C controllers are accessed through MMIO and
these regions need to be added to MMU for proper access.
This also enable MMU for Apollo Lake by default since
serial console is now usable.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Given that the UP Squared has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoCs usually have devices that are accessed through MMIO.
This requires the corresponding regions to be marked readable
and writable in the MMU or else accesses will result in page
faults.
This adds a function which can be implemented in the SoC code to
specify those pages to be added to MMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The integers used for pointer calculation were u32_t.
Change them to uintptr_t to be compatible with 64-bit.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This file consists only of an array of per-CPU IOAPIC ID's that
overrides the weak symbol defined by the architecture.
The IOAPIC IDs are only used when targetting a startup IPI for the
auxiliary right now, but the IDs are the IDs and represent hardware
truth. They should be correct even if unused.
Using the wrong ones also breaks the tests/kernel/mp test, which calls
arch_start_cpu() when not in SMP mode as a deliberate unit test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This test works by starting a bunch of poll events, dropping the test
thread priority, calling k_poll(), and assuming that all the timeouts
that fired woke up high priority threads and thus ran before k_poll()
could return. But that isn't true if you have another CPU that can
run the low priority thread while the last high priority thread
finishes up!
This just isn't SMP-correct. Mark 1cpu.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When PCIe is enabled for UART, the port address is probed during
initialization and is written back into the device config struct.
However, the device config struct is supposed to be const and
read only. This results in page faults when MMU is enabled as
the struct cannot be written into. So fix this by storing port
address in device data struct if a particular UART instance is
of PCIE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Daniel Leung