Commit Graph

3 Commits

Author SHA1 Message Date
Jean-Paul Etienne d1bd80a4a9 riscv32: added the riscv-privilege SOC_FAMILY
added the riscv-privilege SOC_FAMILY, under which all
riscv SOCs supporting the riscv privilege architecture
specifcation shall reside. These SOCs shall notably have
a common base for handling IRQs.

Moved riscv32-qemu under the riscv-privilege SOC_FAMILY

Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-20 23:19:35 +00:00
Jean-Paul Etienne c989f0b408 riscv32: timer: replace riscv_qemu_driver by the generic riscv_machine_driver
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.

The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.

Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-03 19:20:52 +01:00
Jean-Paul Etienne 60030c9a80 boards: added support for the qemu_riscv32 board
The qemu_riscv32 board makes use of:
1) the uart_riscv_qemu driver
2) the riscv_qemu_timer driver

Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:58:09 +00:00