Update a number of boards that have arduino_gpio and arduino_i2c
support in their dts files to show that they support that in the
board.yaml file. This allows coverage on several shield tests that
utilize the tags 'arduino_gpio' and 'arduino_i2c'.
Exlucde stm32mp157c_dk2 from some of the samples right now since the
connector on the board doesn't support A2/A3. Also remove the duplicate
of exluding disco_l475_iot1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The project's README.rst references the support board docs with an URL
that's not working these days (see
https://github.com/zephyrproject-rtos/infrastructure/issues/134) so fix
that URL reference. While looking for other similar linking cases, I
found a hard URL references that should be using :ref: role, and a
release notes reference to a (now) broken link (fixing that in the
/latest/ version of the 1.10 release notes).
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
While trying out the hello_world sample built for QEMU, I was expecting
the sample app to exit and I'd return to a command prompt. Nope. You
need to exit QEMU manually, so add that step to the sample instructions.
Looking around, there are more uses of QEMU like this that could use
this added step after running the sample app.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
For OpenVega board, in the case of the Zero Riscy core,
the flash partition used for the code and data is the
M0 ARM core's 256KB flash region. This is closest to
the RISC core.
The m0_flash node defines where the interrupt vector
is located for the Zero Riscy core, and one needs to
restrict the application so its interrupt vector is
placed accordingly.
Fixes: 34b0516466 ("boards: riscv32: rv32m1_vega:
enable MCUboot for ri5cy core")
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Kumar Gala