Commit Graph

200 Commits

Author SHA1 Message Date
Huifeng Zhang 2c22e83dfb include: arch: arm: Remove aarch32 directory
This commit follows the parent commit work.

This commit introduces the following major changes.

  1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
    to the 'include/zephyr/arch/arm' directory.

  2. Change the path string which is influenced by the changement 1.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Gerard Marull-Paretas 9c961571a2 modules: cmsis: move glue code to modules/cmsis
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).

To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.

All files including CMSIS have been updated.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Jeff Daly f868d391ec Samples: Fix XEC clock control sample code for MEC172x using new GPIOs.
The XEC clock control driver sample code uses enum indexes to offset to
the desired GPIO CTRL register of the package.  These enums are only
used in this example code and are being removed in favor of calculated
indexing into the specific GPIO register memory map.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-08-23 10:06:13 +02:00
Ederson de Souza 91450a4358 soc/arm/microchip_mec/mec17x: Initialise GPIO after ECIA
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the ECIA initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.

This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after ECIA.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-08-15 10:13:37 -07:00
Ederson de Souza 0295edf834 soc/arm/microchip_mec/mec1501: Initialise GPIO after interrupts
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the SOC initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.

This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after SOC.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-08-15 10:13:37 -07:00
Gerard Marull-Paretas 55f5a75c58 pm: remove unnecessary __weak from pm_state_set/pm_exit_post_ops
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas 3d2194f11e pm: introduce HAS_PM
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Manimaran A f6eeb9dc84 soc: MEC1701: Removed Microchip MEC1701
Removed MEC1701 SOC specific sources

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-07-01 12:38:07 +02:00
Manimaran A 0f6cb5edcd drivers: ps2: microchip: Low power and wakeup enabled
ps2 driver updated to support low power and wakeup.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-06-17 07:59:07 -04:00
Carlo Caione 6f3a13d974 barriers: Move __ISB() to the new API
Remove the arch-specific ARM-centric __ISB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Carlo Caione cb11b2e84b barriers: Move __DSB() to the new API
Remove the arch-specific ARM-centric __DSB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Manimaran A f8c8ee65be drivers: pinctrl: Microchip XEC PINCTRL glitch fix
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-05-16 18:52:44 -04:00
Gerard Marull-Paretas a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
scott worley cfcd92b893 soc: mec172x: Fix interrupt unmasking in SoC PM restore path
Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.

Signed-off-by: scott worley <scott.worley@microchip.com>
2023-04-07 13:38:56 +02:00
Scott Worley 5a6cf526ef soc: mec172x: Add hardware debug configuration
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2023-04-04 16:46:07 -04:00
Jay Vasanth b0ce525b90 drivers: espi: Microchip MEC172x eSPI VW initialization update
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-03-23 11:58:26 -04:00
Jay Vasanth f6619a8688 drivers: espi: Update Microchip MEC172x eSPI virtual wires to use DT
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-03-23 11:58:26 -04:00
Manimaran A c42a155988 driver: clock control: Microchip XEC fix missing domain parameter
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-03-23 11:55:19 -04:00
Manimaran A 2b66410675 soc: configuration: microchip SOC Kconfig bug fix
Removed the EEPROM and ESPI configuration from file
Kconfig.defconfig.mec172xnsz. Since it overrides the
setting present in the Device Tree file.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-03-16 12:03:57 -05:00
Fabio Baltieri 1751c8f0f5 soc: mec172x: drop non existing option PINMUX_XEC
Drop the non existing option PINMUX_XEC, this has been removed in

d76f4f2c8a drivers: pinmux: mchp_xec: drop driver

And is currently causing build errors.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-02-27 20:52:51 +01:00
Jeff Daly e32c362038 Microchip: create DTS and Kconfig definition of MEC172x LJ package.
Define extra pins and IP blocks in DTS and Kconfig for the LJ package of
the MEC172x SoC.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-02-27 19:41:11 +01:00
Gerard Marull-Paretas d76f4f2c8a drivers: pinmux: mchp_xec: drop driver
Drop Microchip XEC driver in favor of pinctrl.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-23 16:56:04 -05:00
Jay Vasanth b1cf745828 pm: MEC172x: enable device power mgmt in soc layer
Allow the the SoC to enter deep sleep when CONFIG_PM_DEVICE
is enabled. This will allow to selectively add low power
support for certain drivers like UART and ADC.
The previous checking of ifndef CONFIG_PM_DEVICE was
incorrect. The MEC172x requires the soc power file to perform
some operations when CONFIG_PM_DEVICE is enabled to allow
the hardware to shut down the PLL.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-02-19 20:39:40 -05:00
Jamie McCrae ec7044437e treewide: Disable automatic argparse argument shortening
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-01-26 20:12:36 +09:00
Jay Vasanth 3583421134 soc: microchip_mec: Replace test clock out Kconfig with DT entry
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-12-28 10:43:03 +01:00
Jay Vasanth c7e0d727d7 drivers: clock: Microchip XEC clock driver add MEC15xx support
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x.  MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-12-28 10:43:03 +01:00
Jay Vasanth ed52729a4b drivers: clock: Microchip MEC172x clock control driver support all modes
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-12-28 10:43:03 +01:00
Jose Alberto Meza 5d34891ae0 soc: arm: microchip: mec172x: Correct PECI base address
Use correct device tree entry

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-12-07 09:45:25 -06:00
Jay Vasanth 38ad230aec drivers: pinctrl: Microchip XEC PINCTRL add invert pin
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-11-30 11:29:22 +01:00
Jay Vasanth 4ce502777b soc: arm: mec1501: add debug interface configuration
Move regs configuration from previous pinmux.c to soc layer.
This involves the debug interface, configuring the GPIO bank power
and the test clock out pin.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-11-10 22:39:43 -05:00
Jay Vasanth d0fe965b9f drivers: espi_saf: Add Microchip MEC172x eSPI SAF version 2 driver
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-10-28 14:29:46 -05:00
Jay Vasanth d32d1eb966 soc: microchip_mec: Prepare for MEC172x SAF version 2
Microchip MEC172x eSPI SAF has significant hardware changes
requiring a new SAF configuration structure. In preparation
for the MEC172x we move the current SAF header out of common
to the MEC1501 subfolder, remove an unused and empty common
header and remove includes of the moved headers from MEC172x.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-10-28 14:29:46 -05:00
Jay Vasanth 0976343513 drivers: SPI: MEC172x QMSPI clock fix
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-10-28 14:29:46 -05:00
Jay Vasanth f87acb5bdd soc: arm: microchip: add common mec_gpio.h
add common mec_gpio.h to allow access to common gpio_regs
structure for both mec15xx and mec17xx, used in pinctrl driver

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-10-08 18:32:33 +02:00
Jay Vasanth 64eeef9d57 soc: arm: microchip: update mec1501 soc header
update mec1501 soc.h to include soc_dt.h for pinctrl
related macros

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-09-21 18:05:32 +00:00
Kumar Gala 318c12d17c timer: remove Kconfig.defconfig* setting of timer drivers
Now that timer drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Gerard Marull-Paretas 79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Kumar Gala 3712e44fe0 intc: remove Kconfig.defconfig* setting of interrupt controller drivers
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-01 10:25:36 +02:00
Kumar Gala 9f1f9a4843 peci: remove Kconfig.defconfig* setting of peci drivers
Now that peci drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-16 08:26:11 +00:00
Kumar Gala ff2a1212bf counter: remove Kconfig.defconfig* setting of counter drivers
Now that counter drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-10 10:46:55 -05:00
Kumar Gala 236484456f drivers: kscan: Remove unnecessary Kconfig settings
Have the kscan device enabled in devicetree will now get the driver
enabled by default when CONFIG_KSCAN=y is set.  So we can remove
driver enabling Kconfig values in various Kconfig.defconfig files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-09 23:37:46 -05:00
Jay Vasanth ccb77af3b7 eeprom: Add Microchip eeprom driver skeleton
Prepare for Microchip eeprom driver addition. Update
dtsi, kconfig, cmake and relevant soc files for eeprom
driver addition.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-08-04 18:36:18 +02:00
Kumar Gala 7e8a312c6b adc: remove Kconfig.defconfig setting of ADC drivers
Now that ADC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the ADC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-02 15:51:43 -05:00
Kumar Gala 5c57a36f9d i2c: remove Kconfig.defconfig setting of I2C drivers
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-01 18:01:44 +02:00
Jay Vasanth 3e0f738cb2 mec15xx: pinctrl for both mec15xx and mec17xx
Changes to compile pinctrl driver for both mec15xx
and mec17xx. Also add mec15xx pinctrl dtsi

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-08-01 10:28:23 +02:00
Kumar Gala 5b9e0b615c clock_control: remove Kconfig.defconfig setting of clk control drivers
Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control.  Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-29 14:12:12 +02:00
Kumar Gala 65e1c6fb1e pwm: remove Kconfig.defconfig setting of PWM drivers
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 18:43:54 +02:00
Kumar Gala 960f2f1a37 spi: remove Kconfig.defconfig setting of SPI drivers
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 09:49:00 +02:00
Kumar Gala 9a501e0922 serial: remove Kconfig.defconfig setting of serial drivers
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 09:29:24 -05:00
Kumar Gala 600d749cf3 gpio: remove Kconfig.defconfig setting of GPIO drivers
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 08:49:38 +02:00