Setting up the right SPI port, its configuration and max frequency.
Also, setting NANO_TIMEOUTS by default as it is required for delayed
operation inside ADC's driver.
Change-Id: I63b2b872ff858f1d80065a94ba3e2f303d279a67
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Taking the opportunity to set simpler driver names for port 0 and 1.
Change-Id: I994bc43daaf6bc43b0dad564a72577c874f72d2d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
*_PORT_1_* not *_PORT_0_* obviously.
Change-Id: Idefad40c25b4ad54d9558355daab224bc634c2e7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Galileo SPI interrupt is of type level low, thus setting it to this
value in Galileo's defconfig and removing useless entry in Kconfig.
Change-Id: I90bcc74be1a957bf59912d6f8c2234cfa4fe2329
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Kconfig can't set the default for a choice, so it has to be done
using select.
Change-Id: I1d952eb48a7bcda79b4f8ff475110c7430be7b4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
PCI information and integration of designware's gpio controller
with shared irq.
Change-Id: I80c7fed35ff328e06d87ebad3e2f68fdd6f5672e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Since the console is not yet setup, there will be nothing to be printed
out. Also, it adds a dedicated init function which is only useful for
it. Instead, debugging PCI enumeration can be simply done in application
side.
Change-Id: Ia8384caa97d43f0bc4300ecf36bc11d1b8bd5581
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
As long as PCI_ENUMERATION does not work for all IP block, let's provide
pre-configured base address registers for ns16550 on Galileo.
Once PCI_ENUMERATION will be fixed, such pre-configured settings will
not be used at runtime.
Change-Id: I514b3a5759e3af04132c7801f37033108a7b279b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Providing the right settings through Galileo's Kconfig.
Change-Id: Ia5339eb90cb98d7dde3be0493bcfd9a6b6db60ed
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.
Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Perform configuration of the shared IRQ has to be done earlier,
as the config code masks the interrupt by default. If configuration
is done after shared_irq_enable() is called, the interrupt is
effectively masked. So move the init level a bit earlier.
Change-Id: Ic7f059628e3cf122d323513e171c7d1a09e5d4a6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IOAPIC driver resets all interrupt vectors, so any configuration
has to be done after that. Move the HPET IRQ config to later init
level so we are sure that the configuration is being done.
Change-Id: Id169461cce15252f7fb77e9c07961300233f3344
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With the typos, IRQ triggering conditions are not set correctly.
Change-Id: I0698ce69c3368411a2f91a32ac27608e9f1de252
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This expands the Galileo pinmux driver to configure the GPIOs
on the DesignWare IP block, and the core/resume wells on
the legacy bridge.
Change-Id: Ia1df4b6fd3b104f08563fe9eab93f01efbb53b66
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This enables all the GPIO blocks, and pin muxes on Galileo Gen2
board. GPIO and I2C are now sharing one interrupt line so both
can now get interrupt driven events.
Change-Id: I31a4823abba84539ce5d1cc84e85b7dc335cf831
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DesignWare GPIO and I2C are PCI devices which share the same
IRQ line. This patch enables the shared IRQ support for I2C. GPIO
support is to be followed.
This also enables I2C for nanokernel on Galileo.
Change-Id: I66681d71899914bdcb35c4af649d077ffb8d7970
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On some platforms (e.g. Galileo), the I2C controller is on PCI bus,
which shares IRQ with other devices (GPIO on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: Id4e4714aed37c2893d0ffe9ed1e4edaabb338121
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the code to setup the IO-APIC for shared IRQ.
The code to enable shared IRQ with GPIO and I2C will follow.
Change-Id: I6e7de69f83bf7f1dd0da0571dbcb417beb2c232b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt selectionss are no longer specific to a particular
controller (e.g. I2C_DW_0), but apply to all controllers on
the platform.
[DL: Extracted these changes into their own patch, instead of
being squashed with others. Also modified the Kconfig
options to move them into proper position.]
Change-Id: Idc7ac9769e947447b868dccf772a95dbb5fc8021
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This adds the default config option to enable the I2C controller,
for both nanokernel and microkernel.
Note that choices in Kconfig cannot have default values in Kconfig,
so it has to be done in defconfig instead.
Change-Id: I2ac0c880629db68e5b9a6bf61e49939ab7418a89
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the Kconfig option to specify default configuration
for the I2C controller during driver initialization.
During boot, the controller needs to be configured before
communication to slave devices can start. After boot,
an app can re-configure the controller if needed.
Change-Id: I7bf252f75a31943ae444e4d914f3a9a1a3f3d91f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This macro is legacy from an early implementation of the init system
before the pure level was split into early and late phases remove it
now to avoid confusion going forward.
Change-Id: I6720874c840c9e14888fd6f411a8182e7420ca29
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
[DL: changed mapping, and to set GPIO directions.]
Change-Id: I4153c5565b341215998645377eaad0d91da4febf
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The default values for the platform will be used when running
make *_defconfig instead of hardcoding them in the defconfig directly.
Change-Id: If2945cc11cfca787c2b93a96b502650f1dddd29d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Tomasz Bursztyka