Fix the following dts warnings:
up_squared.dts_compiled: Warning (simple_bus_reg): /soc/gpio@0:
simple-bus unit address format error, expected "d0c50000"
up_squared.dts_compiled: Warning (simple_bus_reg): /soc/i2c@91528000:
simple-bus unit address format error, expected "9158000"
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Zephyr configuration system uses many different files in many
different formats. It makes it a lot easier for users to understand
what these files do if when we use the correct file extensions.
To this end we rename the dts.fixup files to the correct file
extension '.h'.
This is a breaking change for out-of-tree fixup files. Such files will
be detected and given an appropriate error message.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The i2c drivers now consistently select HAS_DTS_I2C, so we no longer
need to select it at the board level.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Sets the HPET timer frequency (enabled by default) to 19.2MHz.
And also sets the local APIC timer frequencies according to
the SoC variant.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are currently three SoC variants for the UP Squared board:
Pentium, Celeron and Atom. This adds a board option to specify
for which variant is being built.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Now that we have a common DT_SIZE_K macro use it instead of defining
__SIZE_K eveywhere. We also have DT_SIZE_M, so use that in a few
places as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The board config has been verified to boot with serial console
on the Atom version of the UP Squared board. So the references
to Pentium/Celeron can be removed. Moreover, add some notes on
BIOS settings, as it may change the MMIO addresses for various
IP blocks.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add the necessary bits to enable the I2C controllers on
the UP Squared board. Only the ones exposed through the HAT
connector(s) are enabled by default.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a primitive board configuration for the UP Squared board
containing Apollo Lake based Pentinum and Celeron SoC. This has
been tested on model UPS-APLP4-A10-0432.
This starts from the minnowboard configuration, and document
from galileo.
Origin: Original
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Kumar Gala