The Keyestudio CAN-BUS Shield (KS0411) is equipped with a Microchip
MCP2551 CAN transceiver with a maximum bitrate of 1Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The DFRobot CAN BUS Shield V2.0 is equipped with a NXP TJA1050 CAN
transceiver with a maximum bitrate of 1Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The NXP TWR-KE18F development board is equipped with a NXP MC33901 CAN
transceiver with a maximum bitrate of 1Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The Atmel SAM E70(B) Xplained development board is equipped with a
Microchip ATA6561 CAN transceiver with a maximum bitrate of 5Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The NXP RDDRONE-FMUK66 development board is equipped with dual NXP
TJA1042 CAN transceivers with a maximum bitrate of 5Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The Renesas R-Car H3ULCB development board is equipped with a TI
TCAN332G CAN transceiver with a maximum bitrate of 5Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The Olimex OLIMEXINO-STM32 development board is equipped with a
Microchip MCP2551 CAN transceiver with a maximum bitrate of 1Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The Olimex STM32-P405 development board is equipped with a TI SN65HVD230
CAN transceiver with a maximum bitrate of 1Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The NXP MIMXRT10xx/11xx EVK boards are equipped with NXP TJA1057 CAN
transceivers with a maximum bitrate of 5Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The NXP LPCXpresso55S16 development board is equipped with a NXP TJA1044
CAN transceiver with a maximum bitrate of 5Mbit/s.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the can_set_bitrate() function to can_common.c as it is getting
quite long for a static inline function.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for getting the maximum supported bitrate in bits/s for CAN
controller/transceiver combination and check that a requested bitrate is
within the supported range.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This contains accessor macros for getting the maximum bitrate supported
by a CAN controller/transceiver combination.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add generic devicetree bindings for simple CAN transceivers.
Always-on CAN transceivers are considered passive and just provide a
maximum supported bitrate.
Active CAN controllers can typically be controlled by the MCU via either
SPI, I2C, or GPIO. Common GPIO controlled CAN transceivers provide
either a stand-by or an enable pin (or both) for controlling the state
of the CAN transceiver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for the new pinctrl API to the nRF PWM driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QDEC driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the DMIC driver that handles
the nRF PDM peripheral. Update code of the driver and the related
devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF I2S driver. Update code
of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Test were executed on single CPU only and with qemu_cortex_a9
excluded. Removing those limitations after fixes.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Seen failures on some platforms. No harm to relax the
check for test timeout.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Delay start of threads and timer to ensure that setup
is completed. Especially, vital on multiple CPUs.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
TCP module can report EAGAIN in case TX window is full. This should not
be forwarded to the application, as blocking socket is not supposed to
return EAGAIN.
Fix this for sendmsg by implementing the same mechanism for handling TX
errors as for regular send/sendto operations.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
In 9170977 build-time version header generation was added. The test
for .git assumes this file to be a directory. In the case of git
submodules, .git is a regular file that in its contents points to
the actual git database for the submodule. This is a way to have
symlink like behaviour even on file systems that do not support
themselves support symlinks.
This consults git as to what the correct git database directory is,
in case the .git file is indeed a regular file, and adjusts the
git_dependency variable accordingly.
Fixes#43503
Signed-off-by: Frank Terbeck <ft@bewatermyfriend.org>
I introduced some errors during the gpio_dt_spec/i2c_dt_spec conversion
process. This patch fixes the issues so that driver builds.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some build configurations in direction finding samples
sample.yaml didn't have harness=bluetooth. That enables
these configurationsto be be executed on hardware by
CI. Those runs end causing CI failures.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Add a 4k indentity mapping in the MMU for the Processor System GPIO
controller if the parent device node is enabled in the device tree.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Bindings for the Xilinx Processor System GPIO controller, both for the
parent controller device as well as the GPIO pin bank child devices.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add the parent controller device node plus the child nodes for all
GPIO pin banks managed by the GPIO controller to the device trees
of the Zynq-7000 and ZynqMP SoCs.
Device base addresses, IRQ lines, number of banks, number of pins
per bank and bank descriptions taken from the Zynq-7000 TRM (Xilinx
document ID ug585), the Zynq UltraScale+ TRM (Xilinx document ID
ug1085) and the Zynq UltraScale+ Devices Register Reference (Xilinx
document ID ug1087, web-based document).
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO
controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs.
The driver is split up into source and header for a parent controller
device and source and header for 1..n child GPIO pin bank devices.
The parent device driver takes care of IRQ handling, the GPIO pin bank
driver provides pin / bank access according to the API defined by the
GPIO subsystem.
More than one device for this type of GPIO controller is required as
it provides access to a number of GPIO pins well in excess of the 32
pins addressable by the current GPIO API (whereever parameters or
return values come in the form of a bit mask):
- Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks.
- ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
add dtsi settings for rt series
dtsi use gpr to replace pinmux
nxp iomuxc has gpr which has more settings than mux and io settings
current solution is to export gpr separately and access then directly
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Henrik Brix Andersen