Several paths are checked for existence before added as global Zephyr
include path.
The existence check was needed because some tooling emit warnings on
non-existing paths.
Only few SoCs are using those pre-defined paths, yet this code runs
for all SoCs. The principle originates back from Kbuild days, and with
CMake it's more common and generally more visible to let the CMake code
defining libraries to specify include paths.
Furthermore it appears that several SoC implementation following the
<soc-path>/include was unaware that the path would be automatically
added as include path, cause they contain lines like:
zephyr_library_include_directories(include)
Remove pre-defineds path except the `<SOC_PATH>` path, which is
guaranteed to exists.
This simplifies the CMake logic in the top-level Zephyr CMakeLists.txt
file.
This cleanup further prepares for future work where SoCs need not to
be organised under architectures which is important for multi-arch SoCs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This patch contains small refactor of lpsram init function (defines
registers and adds new macro).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The symbol _end is used to indicate the start of heap in
the common libc malloc code. On ACE, heap is in uncached
area. However, _end was in the cached area while end of
heap is in uncached area. This resulted in incorrect
calculation of heap size. So move _end into uncached
area so correct heap size can be calculated.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Updating value of WOVRCO request bit in CLKCTL register according to the
documentation. Previus value was mask used for clock enabling.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Created set of new functions for configure fir coefficients with support
for packed format. This allowed to make the dai_dmic_set_config_nhlt
function simpler.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
All fir filters have an identical set of registers so their definitions
were combined to simplify the code. From the dai_dmic_set_config_nhlt
function, a duplicate piece of code responsible for configuring fir was
separated into a new function.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
All PDM controllers have the same set of registers. Their definitions have
been merged to simplify the code.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Use WAIT_FOR to wait for core power changes to be reflected
in status registers. If core power state does not complete in
10ms, k_panic() is raised.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
With gcc from the zephyr sdk and -Wold-style-declaration is giving this
output:
zephyr/arch/arm/core/aarch32/cortex_a_r/fault.c:101:1: warning:
'inline' is not at beginning of declaration [-Wold-style-declaration]
101 | static void ALWAYS_INLINE
z_arm_fpu_caller_save(struct __fpu_sf *fpu)
| ^~~~~~
I searched to all of the source code to find these further occurances
where inline is not at the beginning of a function declaration.
Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
File was using stdint.h defined types without including and caused a
build error depending on include ordering.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add an option to control whether or not hpsram banks should
be switched off during the power down. This is particular useful
when running tests because we don't want to lose the contents
of the memory window before we capture it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The clock rates for ACE series of Intel Audio DSP have changed.
The values come from the SOF project in their board configs.
CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test
can pass.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.
The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.
Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.
Signed-off-by: Keith Packard <keithp@keithp.com>
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The ifdefs in in dmic headers is getting out of control and makes
maintainence very ddifficult, especially when having to maintain out of
tree SoCs sharing the same data and information.
Keep header clean and per SoC and share some common registers in one
place instead avoiding confusion and making it easier to read and
maintain.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
The end of the heap should be the same as _heap_sentry. The current end
marker just covers the range of memory that is explicitly put in
.heap_memand not account until the end of L2_SRAM_BASE +
L2_SRAM_SIZE memory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The macro HW_STATE_CHECK_DELAY represents the number of usec to
busy-wait when waiting for a h/w register state change. This value
has been lowered by 75% to correct a couple of issues related
to Power Management (PM).
1. This resolves a kernel.timer.tickless test failure (see
tests/kernel/timer/timer_api) on the LNL simulator where the test
was taking too long to wake after sleeping for 50 ticks. This
was tracked down to the xtensa SOC power management code where
it was performing a busy wait of 256 usec, which was equivalent
to 2.56 ticks.
2. Furthermore, this delay of 256 usec contradicted the information
in the DTSI (see power-states for d0i3) which states that the
"exit-latency-us" is 100 usec. Reducing this value to 64 helps to
keep that in line.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
To enable IMR on LNL platform new header added to
support context save/restore must be added also to LNL.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Torsten Rasmussen