If the `divider-int-0` or variations of these for each channel properties
are not specified, or if these is 0,
the driver dynamically configures the division ratio by specified cycles.
The driver will operate at the specified division ratio if a non-zero
value is specified for `divider-int-0`.
This is unchanged from previous behavior.
Please specify ``divider-int-0`` explicitly to make the same behavior as
before.
In addition, the default device tree properties related to the division
ratio have been removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Title of the document was wrong, image info was missing, and a bunch of
other formatting issues.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- update the EVK's board.cmake, making linkserver the default runner
- update the board's document file
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Some tests are failing on nrf54h20 cpurad in non-obvious manner
because of this memory region being too small.
Instead of adding overlays to each individual application,
make this region larger at expense of cpuapp equivalent.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add netif:eth to twister yaml for frdm_rw612
Exclude from wifi test because of binary blob requirement
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This inverts x and y axes as reported by stmpe811 driver for stm32f429i.
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This adds zephyr,touch property to boards with touch controllers, analogous
to `zephyr,display`.
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The sample is supposed to help examine the issues with touchscreen.
It draws a plus in last touched position.
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
As in all other esp32-based boards, APPCPU
does not require to have MINIMAL_LIBC as default libc.
In the past, that was required due to memory constraints,
which is not the case anymore.
This fixes build issues in `tests/lib/c_lib/common`.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Version 2 of the ADAC interface implemented by secure domain firmware
changes the ADAC RESET command used in the custom reset handling in
the JLink support scripts. The command has been split into two
commands, RESET and START, and has different semantics from
the previous RESET command. The new RESET command resets both the
application and radio domains without starting the CPUs again, and the
START command must then be used to start the CPUs.
Update the JLink support scripts for nrf54h20dk/nrf54h20/cpuapp,
nrf54h20dk/nrf54h20/cpurad, nrf9280pdk/nrf9280/cpuapp and
nrf9280pdk/nrf9280/cpurad so that they read out the ADAC interface
version from the device and use the newer commands if ADAC version 2 is
detected. If the version is lower than 2, the legacy implementation is
used.
Also improve the CTRL-AP MAILBOX transaction implementation
to avoid the need for arbitrary sleeps or unnecessary polling of
the MAILBOX. This should improve stability when using the script.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Move the process of replacing numerical values with macros to
the header, and set the division ratio in a numeric without
using macros in the device tree.
Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DeviceTree typically references the clock source using the `clocks`
property defined in `base.yaml`, so we'll change it to this.
Also delete the custom clock source definitions in
`renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and
`renesas,ra-cgc-pll.yaml`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
dcache-alignement needs to be defined for ipc to have
consistent memory organization on both endpoints, when
shared memory is cacheable. nrf54h20 and nrf9280 are
using cacheable shared memory.
This is applied for ipc with icmsg backend.
Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
Updating PhyBOARD Polis docs after enabling ECSPI
and CAN support on that board.
Add additional information what to do if
using Linux and Zephyr simultaneously.
Signed-off-by: Peter Fecher <p.fecher@phytec.de>
Configures ECSPI devices in devicetree including connected
mcp2518 (CAN FD).
Configures pinctrl for board.
Enables spi support in board files.
Signed-off-by: Peter Fecher <p.fecher@phytec.de>
Add a new revision for nRF54H20 DK: 0.9.0. This new hardware spin contains
the final nRF54H20 SoC. Treat it as the default, including twister.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The current DK is labeled as revision 0.8.0. Until now, no revisions were
needed, but a new hardware spin is coming, so we'll need to keep at least
two revisions in the near future until the final one becomes the default.
Prepare the board for that scenario. Note that the "old" nRF54H20 SoC is
now nRF54H20 EngB.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Fixes MCUBoot Serial Recovery compilation error
"Serial recovery/USB DFU button must be declared
in device tree as 'mcuboot_button0'"
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Front picture was listed twice, despite the back picture
(max32666fthr_img2.jpg) actually being checked into the repo, so switch
to that one.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
For all STM32 boards that define an asynchronous clock for ADC, specify
which clock is to be used in the clock node.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
One needs the 32bit version of the SDL development library when
building for 32bit native_sim, and for the 64bit native_sim the
64bit version. Let's clarify this.
Also fix the SDL2 link.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
HEAP_MEM_POOL_ADD_SIZE_BOARD is not a zephyr-defined entry and
should be placed into Kconfig instead of Kconfig.defconfig.
This PR moves that entry for all ESP32-based boards accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add documentation about supported displays on this board, as the list is
getting rather long and each display has its own bespoke connection
requirements.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable the rd_rw612_bga board with the LCD_PAR_S035 shield. This shield
cannot be connected directly to the board, but the connection can be
made with a set of jumper wires.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The LCD_PAR_S035 display module shares the reset pin between the display
module and the touchscreen controller. The touchscreen controller needs
the reset pin to be toggled low during boot in order to select the
expected I2C address. However, the reset sequence must occur before the
display is initialized. To enable this, set a custom INPUT driver init
priority when using this display module, so that INPUT drivers start
after MIPI DBI drivers but before DISPLAY drivers.
Since the reset sequence is now operating as expected, we no longer need
to use the alt-addr probing method. This method was previously only
working correctly because boards using this display were configuring
the display INT pin using the pin control API prior to resetting the
display, so when the display was reset it would select the alt-addr
I2C address.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Although the parallel mipi dbi mode pinout used for the LCD PAR S035
display is specific to NXP boards, the definition of the display is
generic, and does not require NXP-specific parallel mipi dbi IP.
Therefore, rename the MIPI DBI node for this display from
`nxp_flexio_lcd` to `zephyr_mipi_dbi_parallel`. The gpio-nexus node name
is unchanged, as the pinout it describes is specific to NXP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The stm32h7 nucleo 144 boards (ref MB1364)
have the LD2 on PE1 pin (not PB7). This commit change this
in the doc. Board DTS are correct.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
MAX32662EVKIT board has CFAF128128B1-0145T display which
is 128x128 graphic display.
This commit enable mpi dbi display support with LVGL graphic library.
Pin connection of display is 3wire mode
SRAM size increased to be fit with lvgl example.
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Add rimage support for the i.MX95 EVK M7-based DDR board
variant. This is only required when running SOF.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, OpenOCD doesn't support the cc1352p7.
There are two open PR adding its support to Zephyr's OpenOCD[1]
and upstream OpenOCD[2].
Until this gets merged, we need to use a downstream version of OpenOCD.
This updates the documentation to explain where to find it and how to
use it.
[1] https://github.com/zephyrproject-rtos/openocd/pull/65
[2] https://review.openocd.org/q/owner:abailon%2540baylibre.com
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
This is in preparation for adding another SoC where qemu_xtensa
is no longer valid choice. So use qemu_xtensa/dc233c as it is
the same as the old qemu_xtensa.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For the parts of the simulator which are dedicated for the native
platforms (POSIX arch based):
* Refactor the parts that interacts with the host, so it is possible to
use it also with embedded libCs
* Enhance it with more options to allow:
* Keeping the content just in RAM
* Erasing the EEPROM file at exit
* Clearing the file at boot
* Also show in the command line help the default file name.
As part of this:
* Update the kconfig dependencies, so we allow building it with other
C libraries in the native targets
* Update the table in the native_sim docs to indicate all C libraries
are supproted now
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The RT1170 MIPI DPHY requires a faster clock frequency setting for
the MIPI DPHY, or the pixel packet counts for the HFP, HBP, and HSA will
be incorrect, and the DSI transfers will stall. Raise the target DPHY
clock frequency to resolve this.
Fixes#78299
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds a virtual target using the `cortex_r8_virtual` SoC.
It can be used for testing purposes and a starting point to add new R8
platforms.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
TOKITA Hiroshi