Removed duplicated configuration items for CONFIG_ARM64_VA_BITS and
CONFIG_ARM64_PA_BITS, and modify them to be 36bit as SoC supports up
to 34-bit address.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
fvp_base_revc_2xaemv8a supports up to 2 clusters and 8 cores, each
cluster has 4 cores.
Due to zephyr supports up to 4 cores, for now, I add another 3 cores,
they all belong to cluster0.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. Enable all cpu cores in soc dts and disable unused core in board dts.
2. Use default irq priority for uart interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. In order to figure out board name easily for a-core and m-core, add
a53 suffix in a-core board names.
2. Will support two board configures: one for non-smp and one for smp, both
of them can boot from uboot command line or load into Jailhouse inmate,
so remove Jaihouse suffix from board names.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. In order to figure out board name easily for a-core and m-core, add
a53 suffix in a-core board names.
2. Will support two board configures: one for non-smp and one for smp, both
of them can boot from uboot command line or load into Jailhouse inmate, so
remove Jaihouse suffix from board names.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Now that images are scaled up to the ~width of the page, there's no need
to scale. Also center images to make things prettier.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The boards folder uses ~142.8 MB, being the largest in the repository.
This is due mostly to board images, which are in most cases not
optimized for web content. This patch tries to address this problem by
converting all pictures to JPEG (quality 75) and by adjusting its size
up to 750 px (the width of the documentation content). Images that
specified a fixed width in rst files are converted down to that value
instead.
With this patch, folder goes down to ~53.5 MB from 142.8 MB (-~63%).
Note that this patch introduces a new set of binary files to git
history, though (bad).
The process has been automated using this quickly crafted Python script:
```python
from pathlib import Path
import re
import subprocess
def process(doc, image, image_jpeg, size):
subprocess.run(
(
f"convert {image}"
"-background white -alpha remove -alpha off -quality 75"
f"-resize {size}\> {image_jpeg}"
),
shell=True,
check=True,
cwd=doc.parent,
)
if image != image_jpeg:
(doc.parent / image).unlink()
for doc in Path(".").glob("boards/**/*.rst"):
with open(doc) as f:
content = ""
image = None
for line in f:
m = re.match(r"^(\s*)\.\. (image|figure):: (.*)$", line)
if m:
if image:
process(doc, image, image_jpeg, size)
image = Path(m.group(3))
if image.suffix not in (".jpg", ".jpeg", ".png"):
content += line
image = None
continue
image_jpeg = image.parent / (image.stem + ".jpg")
size = 750
content += (
f"{m.group(1)}.. {m.group(2)}:: {image_jpeg}\n"
)
elif image:
m = re.match(r"\s*:height:\s*[0-9]+.*$", line)
if m:
continue
m = re.match(r"\s*:width:\s*([0-9]+).*$", line)
if m:
size = min(int(m.group(1)), size)
continue
content += line
if line == "\n":
process(doc, image, image_jpeg, size)
image = None
else:
content += line
with open(doc, "w") as f:
f.write(content)
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adding logos to the documentation doesn't add much value and increases
repository size (due to images).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
We had a bunch of QEMU logos embedded in all QEMU boards. Logos do not
add much value to the documentation, so just delete them.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that DMA drivers are enabled based on devicetree we can
remove any cases of them getting enabled by *.conf files.
Signed-off-by: Kumar Gala <galak@kernel.org>
This is a single-CPU board that would normally be expected to have
icount enabled, but doesn't. So it sees a ton of false positive test
failures due to timing skew, which (for still-poorly-understood
reasons) have recently become much worse in CI.
It looks like this got held back by a qemu bug where the emulator
would ignore SIGTERM, but that can be worked around in twister.
Turn it on. The SHIFT value of 4 matches the 62.5 MHz simulated
clock exactly, which is pleasing.
Signed-off-by: Andy Ross <andyross@google.com>
We drive the default setting of CONFIG_PM_CPU_OPS_PSCI via devicetree
so there is no need to set CONFIG_PM_CPU_OPS_PSCI in defconfig files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that serial drivers are enabled based on devicetree we can remove
any cases of them getting enabled by *defconfig and proj.conf files.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit introduces driver for granting access for own grant
table and for mapping/unmapping foreign gref. Grant tables are used
for data exchange between Xen domains via shared memory page(s) (e.g.
for sharing ring buffer with driver data) This functionality is
widely used and needed for implementing PV backend/frontend drivers.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property. Update the dts bindings to not require it and
remove setting of the label property in dts files.
Signed-off-by: Kumar Gala <galak@kernel.org>
The FVP runs extremely slowly (20 to 30 times slow) when we enable 4
cores. Disabling the cache_state_modelled can make it a little bit
quicker.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The tests/kernel/mem_protect/syscalls/ and tests/kernel/smp/ run too
slow on fvp_baser_aemv8r_smp. Increase the timeout_multiplier to 8 for
fvp_baser_aemv8r_smp.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add partial pin control support for the imx8mp. Since the UART driver is
not currently enabled, pin control cannot be tested on this platform.
Therefore, only the DTS definitions required to set the pinmux options
are present for this platform, and are not being applied (since
CONFIG_PINCTRL=n).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control group definitions for all iMX application cores. This
commit does not enable pin control for any iMX cores, as the SOC level
support is not present, but does define the require pin mux settings for
all boards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order to bring consistency in-tree, migrate all boards code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
fvp-baser-aemv8r has four pl011_uart devices and all of then have
been added in this patch.
only uart0 and uart1 are enabled as default in fvp_baser_aemv8r.dts
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Fix SRAM base address to 0x0 and set the size to 128M
Fix FLASH base address to 0x88000000 and set the size to 64MB
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Jiafei Pan