4 Commits

Author	SHA1	Message	Date
Flavio Ceolin	67ca176754	headers: Fix headers across the project ... Any word started with underscore followed by and uppercase letter or a second underscore is a reserved word according with C99. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>	2018-09-17 15:49:26 -04:00
Nathaniel Graff	45d5d5db48	boards: riscv: Convert HiFive1 to DTS ... Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and riscv,plic0. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	2018-08-13 18:35:38 -05:00
Karol Gugala	1765d75ff4	riscv32: riscv-privilege: Microsemi Mi-V support ... This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com>	2018-06-20 11:57:07 -04:00
Karol Gugala	23a5b5d171	riscv32: riscv-privilege: integrate common code ... This commit moves code from fe310 platform into RISC-V privilege common folder. This way the code can be reused by other platforms in future. signed-off-by: Karol Gugala <kgugala@antmicro.com>	2018-06-20 11:57:07 -04:00