The various macros to do checks in system call handlers all
implictly would generate a kernel oops if a check failed.
This is undesirable for a few reasons:
* System call handlers that acquire resources in the handler
have no good recourse for cleanup if a check fails.
* In some cases we may want to propagate a return value back
to the caller instead of just killing the calling thread,
even though the base API doesn't do these checks.
These macros now all return a value, if nonzero is returned
the check failed. K_OOPS() now wraps these calls to generate
a kernel oops.
At the moment, the policy for all APIs has not changed. They
still all oops upon a failed check/
The macros now use the Z_ notation for private APIs.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
TimerHandle->Init.Period is used to initialize TIMx ARR register. The
timer will count from 0 up to ARR including, thus it will tick
(ARR + 1) timers per period. As the "period_cycles" variable holds the
number of desired ticks, the ARR register is computed as
ARR = period_cycles - 1
Update the code to reflect this relationship. Otherwise the timer will
count one more tick for each period, leading to a wrong PWM frequency.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
When we called DEVICE_AND_API_INIT for PMW3, we accidently had
pwm_stm32_2 instead of pwm_stm32_3.
Fixes: #6625
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Normally a syscall would check the current privilege level and then
decide to go to _impl_<syscall> directly or go through a
_handler_<syscall>.
__ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will
make all the system calls from the driver files directly link
to the _impl_<syscall>. Thereby reducing the overhead of checking the
privileges.
In the previous implementation all the source files would be compiled
by zephyr_source() rule. This means that zephyr_* is a catchall CMake
library for source files that can be built purely with the include
paths, defines, and other compiler flags that all zephyr source
files uses. This states that adding one extra compiler flag for only
one complete directory would fail.
This limitation can be overcome by using zephyr_libray* APIs. This
creates a library for the required directories and it also supports
directory level properties.
Hence we use zephyr_library* to create a new library with
macro _ZEPHYR_SUPERVISOR_ for the optimization.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Driver APIs might not implement all operations, making it possible for
a user thread to get the kernel to execute a function at 0x00000000.
Perform runtime checks in all the driver handlers, checking if they're
capable of performing the requested operation.
Fixes#6907.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Upcoming Nordic ICs that share many of the peripherals and architecture
with the currently supported nRF5x ones are no longer part of the nRF5
family. In order to accomodate that, rename the SoC family from nrf5 to
nrf, so that it can contain all of the members of the wider Nordic
family.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Fix Kconfig help sections and add spacing to be consistent across all
Kconfig file. In a previous run we missed a few.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The default PWM polarity was 'inversed', which is not aligned with the
other PWM drivers. Unfortunately there is not yet an API to define the
default polarity to be used by the driver, but assume that 'normal'
(signal starts high for the duration of the duty cycle) should be the
default.
Signed-off-by: Ricardo Salveti <ricardo@opensourcefoundries.com>
Use "select USE_STM32_HAL_TIM" to select the needed STM32 HAL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
As the nRF5x BLE controller uses TIMER1, TIMER2 and PPI
indices 0-13 (and 14-15, if PA/LNA feature is enabled),
the software based PWM driver needing 6 PPI channels has
to use PPI indices outside the BLE controller used range.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
SoCs outside the Kinetis family can have the FTM module, so move the
HAS_FTM config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Note that 'select HAS_FTM' was previously missing from Kconfig.soc and
is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
RCC_HCLK_DIV1 translates to 0x0 while apb_psc uses the value defined
by CONFIG_CLOCK_STM32_APB1/2_PRESCALER (range from 1 to 16).
Manually check if the defined prescaler is 1 or not and use that to
calculate the correct timer clock.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Add support for TIM3 as it is widely available and pins available via
headers on several devices.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Now that we have an mcux shim driver, remove the old k64-specific
driver. Also remove include/drivers/k20_sim.h, since the old
k64-specific driver was the only thing left using it.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux ftm driver to adapt it to the Zephyr
pwm interface.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Change the common "init with 0" + "give" idiom to "init with 1". This
won't change the behavior or performance, but should decrease the size
ever so slightly.
This change has been performed mechanically with the following
Coccinelle script:
@@
expression SEM;
expression LIMIT;
expression TIMEOUT;
@@
- k_sem_init(SEM, 0, LIMIT);
- k_sem_give(SEM);
+ k_sem_init(SEM, 1, LIMIT);
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Removed the old PWM APIs usage and added support for the new PWM API.
JIRA: ZEP-2018
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for nRF5x series GPIOTE based PWM driver
implementation.
Provides upto 3 pins/channels using one HF timer, two PPI
channels per pin, and one GPIOTE config per pin.
Change-id: I6056b199ec2cff595ba8fea9f659a0338ed4635b
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
After activation of cube based driver support on L4 and F3 series,
this commits performs the clean up of F3 and L4 relative code to
native clock control drivers.
Indirectly, it makes pwm driver supported de facto on F3 series
Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32 pwm driver to support it.
Once supported across the whole family, a clean up will be done.
Change-Id: I2ed38763b706e34ea1dceea50e97ce836dd9e195
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
This is one the series patches that simplifies the driver code by
using the IS_ENABLED macro. This removes the need of the const
variable and the wrapper functions on semaphore APIs.
Jira: ZEP-1251
Change-Id: Ic2df5d04966d2a066478ca3e119f76d24fc4dfb3
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move logging out of misc/ to its own subsystem. Anything related to
logging and any new logging features or backends could be added here
instead of the generic location in misc/ which is overcrowded with
options that are not related to eachother.
Jira: ZEP-1467
Change-Id: If6a3ea625c3a3562a7a61a0ba5fd7e6ca75518ba
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Provide PWM driver for STM32 series F1/F4/L4.
Driver is ported on STM32Cube HAL and should support other STM32
series with minor updates.
Configuration is done so that PWM sample driver could be run on
all nucleo boards supporting PWM driver.
Change-Id: I6522a565451085df932e0eefd8404268380b5bfe
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
This fixes an uninitialized pointer being pass and evaluated by
a subsequent function
This issue was reported by Coverity (CID 150824)
Change-Id: If1f636a44cc675b56e426b1de85895b74ba7105e
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add type cast to prevent overflow.
In the pwm driver function pwm_qmsi_get_cycles_per_sec(),
there is a multiplication which takes ticks_per_us (32 bit
unsigned integer) and USEC_PER_SEC. Practically, overflow
will not happen, since the sys clock is not that high. But,
it can trigger an overflow alarm by automatic tools.
Change-Id: I67e6f6a4763e62f6674fcdd364880d93829e739e
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This commit updates the pwm_qmsi driver by removing the temporary Zephyr
save/restore context implementation and using the new QMSI APIs.
Jira: ZEP-1008
Change-Id: Ic92feeb906539f506eb521b7302f8cf5af3edc64
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
Implement qmsi shim driver based on the new API interfaces.
Recently, a RFC was sent and discussed on the re-design of
PWM interfaces. A API change was already posted.
The API new design will deprecate all existing APIs and three
new APIs will be added. The new APIs are pwm_pin_set_cycles,
pwm_pin_set_usec and pwm_get_cycles_per_sec. Pwm_pin_set_cycles
and pwm_pin_set_usec will rely on two driver functions to set
the period and pulse width. This change is to implement the
driver functions pwm_qmsi_pin_set and pwm_qmsi_get_cycles_per_
sec.
Jira: ZEP-745
Change-Id: I39bb973f8c5b19cb7dbd496d10e7f0b6735efc12
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.
Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
When user wants to set all the PWM ports in one call,
pwm_qmsi_set_values() should call __set_one_port() for
each PWM port. The current pwm_qmsi_set_values() will
return after setting the first PWM port. It's illogical.
Change-Id: I5776bf636c2dc58683c629e26f72fca335e781db
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
Andrew Boie