OrgZephyr/zephyr
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3 Commits

Author SHA1 Message Date
Ederson de Souza a6a9a35d0a doc/hardware/arch: Add RISC-V information 
This is just a stub with bits of information about RISC-V support on
Zephyr, that can and should be improved over time.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
 2022-07-02 14:16:39 +02:00
Jordan Yates f2d80c1b11 doc: guides: semihost: added 
Add a guide section on how to use semihosting with an example code
section on opening a file to read data from it.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
 2022-04-21 13:04:52 +02:00
Anas Nashif df033b28de doc: create new Hardware Support section 
Add new hardware section and move all related content from old
structure.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2022-04-07 16:35:19 +02:00