define the irq handler in case of DMA V1 or V2,
for the stm32x soc series
with DMA V1 raise Fifo Error if enabled
with V2, handle the Global Interrupt
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The DMA driver of stm32 used to use `stm32_dma_enable_fifo()`,
which is located in dma_stm32_v1.c to set DMDIS bit, enable
interrupt generation and set FIFO threshold. Now since FIFO
threshold is initialized with `stm32_dma_get_fifo_threshold()`
and interrupt generation is also configured in dma_stm32.c, this
function will only have one job, to configure FIFO mode.
We can add FIFO mode operation in dma_stm32.c directly and
remove it from dma_stm32_v1.c.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Kumar Gala