This commit follows the parent commit work.
This commit introduces the following major changes.
1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
to the 'include/zephyr/arch/arm' directory.
2. Change the path string which is influenced by the changement 1.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Warning callback by default is configured to happen
at the same time as reset, which results in unexpected
behavior from the point of view of Zephyr API. Return
-ENOTSUP from install_timeout if trying to set up
callback with 0 warning time, and add kconfig to configure
the warning time.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
i.MX RT SoC have some pins related to the watchdog.
For example, iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb allows WDOG1_RST_B_DEB
signal to be used as reset source for i.MX RT10xx boards.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
Fix a shadow variable build error:
wdt_andes_atcwdt200.c:112:49: warning: declaration of 'counter_dev'
shadows a global declaration [-Wshadow]
112 | static void wdt_counter_cb(const struct device *counter_dev,
uint8_t chan_id, |
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ wdt_andes_atcwdt200.c:95:35: note:
shadowed declaration is here
95 | static const struct device *const counter_dev = |
^~~~~~~~~~~
Make the outer variable more specific rather than the local one.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add shell commands to setup, disable, install timeout and feed a
watchdog device.
These commands reflect watchdog API.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
Introduce support for NXP FS26 SBC watchdog. Both Challenger and
Simple watchdog types are supported. Only watchdog functionalities of
the device are supported and any other monitoring feature is either not
supported or disabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The OpenTitan watchdog driver is a watchdog driver that can be configured
with two stages: a watchdog "bark", which generates an interrupt, and a
watchdog "bite", which resets the system. The two-stage watchdog can be
enabled by setting CONFIG_WDT_MULTISTAGE=y. Otherwise, the driver
functions as a single-stage watchdog.
A callback function may be set for the bark interrupt through the
wdt setup interface, but will only be used if the two-stage watchdog is
enabled. It must be configured for the first watchdog stage.
The driver controls only the watchdog portion of the OpenTitan AON timer.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
Make sure MFD driver for nPM6001 gets built, and, that watchdog driver
comes later in the init sequence.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a driver for the Xilinx AXI Timebase WDT logic core. This can be
instantiated on various Xilinx FPGA-based platforms such as the
Digilent Arty, although it is not part of the default image used with
the Zephyr board configuration.
The driver can also optionally implement the HWINFO API to allow
determining whether the last system reset was initiated by the WDT.
Since this is a standalone IP core which could be used a variety of
configurations, this support is optional in case the system/SoC it is
used with already implements this support.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
New nrfx release replaces `nrf_wdt_behaviour_t` type
to `nrf_wdt_behaviour_mask_t` enumerator. As a result function
setting behaviour accepts `uint32_t` bitmask of behaviour.
This commit aligns symbols used in SHIM to the ones introduced
with the nrfx release.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
All other watchdog drivers also use POST_KERNEL, and it seems on some
platforms where the TCO watchdog is used not all dependencies are yet set
up by the PRE_KERNEL_1 level.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
rename the function that sets the handler for the nmi.
It should be namespaced and not camel-case:
z_NmiHandlerSet to z_arm_nmi_set_handler
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In the intel_adsp_wdt_isr function was an unused dev_config variable.
The variable was removed. This was caught by the sof CI.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This adds a basic Intel TCO watchdog driver. The driver doesn't support
windowed timeouts (a non-zero window.min value) or callbacks. The driver
currently assumes TCO version 6, which can be found e.g. on Elkhart Lake
and Raptor Lake platforms. The driver also expects the TCOBA base
address to be specified through DTS, rather than doing runtime lookup
(using e.g. ACPI or PCIe).
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add support for the TI TPS382x series. The IC has an input pin which
should be toggled by the processor and a output pin which should be
connected to the RESET input of the processor. The timeout is not
configurable.
This device can be used by devices which does not have any internal
hardware watchdog device.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
An invalid macro name was used to check whether the watchdog device has
configured interrupts. As a result, the interrupt were never configured.
This issue has been fixed.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
New Zephyr WDT driver for TI CC13xx/CC26xx family.
Supports interrupts & MCU soft reset on timeout.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
To follow the IWDG configuration sequence, the timeout install is
just preparing the reload and prescaler parameters.
Then during the iwdg setup the watchdog is enabled and configured
at the same time.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
RP2040 requires watchdog load time in us, but Zephyr
watchdog window values are in ms. Make sure that it is
adjusted to hardware requirements.
Signed-off-by: Marcin Jabrzyk <marcin.jabrzyk@gmail.com>
the watchdog is enabled by the wdt_setup()
coming after the wdt_install_timeout.
Due to PR #44972, the code did not follow that.
This PR fixes the correct other in the sequence.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When using watchdog which doesn't support callbacks (e.g. STM32 IWDG)
it's very useful to have counter based watchdog with shorter timeout.
This way we can gather useful information before IWDG resets SOC.
In above case it's usually not desired to reset SOC when counter
watchdog is triggerd, because we can lose information about reset cause.
For example, STM32 can determine if the reset was caused by watchdog.
Another use case for counter watchdog without SOC reset is to detect
slow code paths.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Some files were using definitions from sys_clock.h, e.g. MSEC_PER_SEC
without including the header.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Huifeng Zhang